[PATCH 1/2] drm/amdgpu/jpeg2: move jpeg2 shared macro to header file

[Leo Liu]

The series are:

Reviewed-by: Leo Liu <leo.lilu at amd.com>

On 2021-09-29 3:57 p.m., James Zhu wrote:
> Move jpeg2 shared macro to header file
>
> Signed-off-by: James Zhu <James.Zhu at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 20 --------------------
>   drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 20 ++++++++++++++++++++
>   2 files changed, 20 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> index 85967a5..299de1d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c
> @@ -32,26 +32,6 @@
>   #include "vcn/vcn_2_0_0_sh_mask.h"
>   #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
>   
> -#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET				0x1bfff
> -#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
> -#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
> -#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
> -#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
> -#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40eb
> -#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
> -#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
> -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET			0x40e8
> -#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
> -#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
> -#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
> -#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40ed
> -#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
> -#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
> -#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
> -#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
> -
> -#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
> -
>   static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev);
>   static void jpeg_v2_0_set_irq_funcs(struct amdgpu_device *adev);
>   static int jpeg_v2_0_set_powergating_state(void *handle,
> diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
> index 15a344e..1a03baa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h
> @@ -24,6 +24,26 @@
>   #ifndef __JPEG_V2_0_H__
>   #define __JPEG_V2_0_H__
>   
> +#define mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET				0x1bfff
> +#define mmUVD_JPEG_GPCOM_CMD_INTERNAL_OFFSET				0x4029
> +#define mmUVD_JPEG_GPCOM_DATA0_INTERNAL_OFFSET				0x402a
> +#define mmUVD_JPEG_GPCOM_DATA1_INTERNAL_OFFSET				0x402b
> +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ea
> +#define mmUVD_LMI_JRBC_RB_MEM_WR_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40eb
> +#define mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET				0x40cf
> +#define mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET				0x40d1
> +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET			0x40e8
> +#define mmUVD_LMI_JRBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40e9
> +#define mmUVD_JRBC_IB_SIZE_INTERNAL_OFFSET				0x4082
> +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_LOW_INTERNAL_OFFSET		0x40ec
> +#define mmUVD_LMI_JRBC_RB_MEM_RD_64BIT_BAR_HIGH_INTERNAL_OFFSET		0x40ed
> +#define mmUVD_JRBC_RB_COND_RD_TIMER_INTERNAL_OFFSET			0x4085
> +#define mmUVD_JRBC_RB_REF_DATA_INTERNAL_OFFSET				0x4084
> +#define mmUVD_JRBC_STATUS_INTERNAL_OFFSET				0x4089
> +#define mmUVD_JPEG_PITCH_INTERNAL_OFFSET				0x401f
> +
> +#define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR				0x18000
> +
>   void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring);
>   void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring);
>   void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,