[PATCH] drm/amd/smu: Increace dpm level count only for aldebaran

[Zhang, Hawking]

[AMD Official Use Only - General]

Hi @Gao, Likun,

Can we replace the asic_type check with ip versioning check?

Regards,
Hawking

-----Original Message-----
From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Friday, April 29, 2022 05:30
To: amd-gfx at lists.freedesktop.org
Cc: Gao, Likun <Likun.Gao at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: [PATCH] drm/amd/smu: Increace dpm level count only for aldebaran

From: Likun Gao <Likun.Gao at amd.com>

Only aldebaran on SMU v13 will get 0 based max level from fw and increment by one, other ASIC will not need for this.

Signed-off-by: Likun Gao <Likun.Gao at amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index cf09e30bdfe0..21b1187028fd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1750,8 +1750,8 @@ int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
        int ret;

        ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
-       /* FW returns 0 based max level, increment by one */
-       if (!ret && value)
+       /* ALDEBARAN FW returns 0 based max level, increment by one for it */
+       if((smu->adev->asic_type == CHIP_ALDEBARAN) && (!ret && value))
                ++(*value);

        return ret;
--
2.35.1