[PATCH 13/32] drm/amd/display: Fix subvp calculations

[Tom Chung]

From: Alvin Lee <alvin.lee2 at amd.com>

[Descriptions]
Missed some brackets in order of operations

Reviewed-by: Samson Tam <Samson.Tam at amd.com>
Acked-by: Tom Chung <chiahsuan.chung at amd.com>
Signed-off-by: Alvin Lee <alvin.lee2 at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 48 ++++++++++----------
 1 file changed, 25 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 759d54843eff..62f7dd94f498 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -432,26 +432,26 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
 	pipe_data->pipe_config.vblank_data.drr_info.use_ramping = false; // for now don't use ramping
 	pipe_data->pipe_config.vblank_data.drr_info.drr_window_size_ms = 4; // hardcode 4ms DRR window for now
 
-	drr_frame_us = (uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000 /
-			(uint64_t)(drr_timing->pix_clk_100hz * 100);
+	drr_frame_us = ((uint64_t)drr_timing->v_total * drr_timing->h_total * 1000000) /
+			(((uint64_t)drr_timing->pix_clk_100hz * 100));
 	// P-State allow width and FW delays already included phantom_timing->v_addressable
-	mall_region_us = (uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000 /
-			(uint64_t)(phantom_timing->pix_clk_100hz * 100);
+	mall_region_us = ((uint64_t)phantom_timing->v_addressable * phantom_timing->h_total * 1000000) /
+			(((uint64_t)phantom_timing->pix_clk_100hz * 100));
 	min_drr_supported_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
-	min_vtotal_supported = (uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us /
-			(uint64_t)(drr_timing->h_total * 1000000);
-
-	prefetch_us = (uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000
-			/ (uint64_t)(phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us;
-	subvp_active_us = (uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000 /
-			(uint64_t)(main_timing->pix_clk_100hz * 100);
-	drr_active_us = (uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000 /
-			(uint64_t)(drr_timing->pix_clk_100hz * 100);
+	min_vtotal_supported = ((uint64_t)drr_timing->pix_clk_100hz * 100 * min_drr_supported_us) /
+			(((uint64_t)drr_timing->h_total * 1000000));
+
+	prefetch_us = ((uint64_t)(phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total * 1000000)
+			/ (((uint64_t)phantom_timing->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us);
+	subvp_active_us = ((uint64_t)main_timing->v_addressable * main_timing->h_total * 1000000) /
+			(((uint64_t)main_timing->pix_clk_100hz * 100));
+	drr_active_us = ((uint64_t)drr_timing->v_addressable * drr_timing->h_total * 1000000) /
+			(((uint64_t)drr_timing->pix_clk_100hz * 100));
 	max_drr_vblank_us = (subvp_active_us - prefetch_us - drr_active_us) / 2 + drr_active_us;
 	max_drr_mallregion_us = subvp_active_us - prefetch_us - mall_region_us;
 	max_drr_supported_us = max_drr_vblank_us > max_drr_mallregion_us ? max_drr_vblank_us : max_drr_mallregion_us;
-	max_vtotal_supported = (uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us /
-			(uint64_t)(1000000 * drr_timing->h_total);
+	max_vtotal_supported = ((uint64_t)drr_timing->pix_clk_100hz * 100 * max_drr_supported_us) /
+			(((uint64_t)drr_timing->h_total * 1000000));
 
 	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
 	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
@@ -545,10 +545,12 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 	struct dc_crtc_timing *phantom_timing1 = &subvp_pipes[1]->stream->mall_stream_config.paired_stream->timing;
 	struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 *pipe_data = NULL;
 
-	subvp0_prefetch_us = (uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) * phantom_timing0->h_total * 1000000 /
-			(uint64_t)(phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us;
-	subvp1_prefetch_us = (uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) * phantom_timing1->h_total * 1000000 /
-			(uint64_t)(phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us;
+	subvp0_prefetch_us = ((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
+			(uint64_t)phantom_timing0->h_total * 1000000) /
+			(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us);
+	subvp1_prefetch_us = ((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
+			(uint64_t)phantom_timing1->h_total * 1000000) /
+			(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us);
 
 	// Whichever SubVP PIPE has the smaller prefetch (including the prefetch end to mall start time)
 	// should increase it's prefetch time to match the other
@@ -557,7 +559,7 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 		prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 				((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
-					(phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)) /
+					((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)) /
 					((uint64_t)phantom_timing1->h_total * 1000000);
 
 	} else if (subvp1_prefetch_us >  subvp0_prefetch_us) {
@@ -565,7 +567,7 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 		prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
 				((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
-					(phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)) /
+					((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)) /
 					((uint64_t)phantom_timing0->h_total * 1000000);
 	}
 }
@@ -618,10 +620,10 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
 
 	// Round up
 	pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-			((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * (phantom_timing->pix_clk_100hz * 100) +
+			((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 					((uint64_t)phantom_timing->h_total * 1000000 - 1)) / ((uint64_t)phantom_timing->h_total * 1000000);
 	pipe_data->pipe_config.subvp_data.processing_delay_lines =
-			((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * (phantom_timing->pix_clk_100hz * 100) +
+			((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 					((uint64_t)phantom_timing->h_total * 1000000 - 1)) / ((uint64_t)phantom_timing->h_total * 1000000);
 	// Find phantom pipe index based on phantom stream
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
-- 
2.25.1