[PATCH v2] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code
Rodrigo Siqueira Jordao
Rodrigo.Siqueira at amd.com
Thu Aug 11 22:38:15 UTC 2022
On 2022-08-11 17:49, Alex Deucher wrote:
> On Thu, Aug 11, 2022 at 3:56 PM Rodrigo Siqueira
> <Rodrigo.Siqueira at amd.com> wrote:
>>
>> We got a report from Stephen/Michael that the PowerPC build was failing
>> with the following error:
>>
>> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
>> ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
>>
>> This error happened because of the function optc3_set_vrr_m_const. This
>> function expects a double as a parameter in a code that is not allowed
>> to have FPU operations. After further investigation, it became clear
>> that optc3_set_vrr_m_const was never invoked, so we can safely drop this
>> function and fix the ld issue.
>>
>> Changes since V1:
>> - Drop optc3_fpu_set_vrr_m_const since it is unused.
>
> FWIW, I upstreamed v1 already. Can you rebase your v2 changes on that?
Hi Alex,
I guess the v1 was not merged into the amd-staging-drm-next. I just
applied the v1 there (waiting for CI result).
I also sent this patch:
https://lore.kernel.org/amd-gfx/CADnq5_OiqWc7REg8CJ_S6UKHoBV0ZgE-+9WO1CexOjk+7ZWeNg@mail.gmail.com/T/#t
Thanks
Siqueira
>
> Alex
>
>>
>> Cc: Alex Deucher <alexander.deucher at amd.com>
>> Cc: Melissa Wen <mwen at igalia.com>
>> Cc: Maíra Canal <mairacanal at riseup.net>
>> Reported-by: Stephen Rothwell <sfr at canb.auug.org.au>
>> Reported-by: Michael Ellerman <mpe at ellerman.id.au>
>> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
>> ---
>> .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 --
>> .../gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 3 -
>> .../gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 1 -
>> .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 77 -------------------
>> .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h | 3 -
>> .../amd/display/dc/inc/hw/timing_generator.h | 2 -
>> 6 files changed, 94 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
>> index d072997477dd..1782b9c26cf4 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
>> @@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
>> REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
>> }
>>
>> -void optc3_set_vrr_m_const(struct timing_generator *optc,
>> - double vtotal_avg)
>> -{
>> - DC_FP_START();
>> - optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
>> - DC_FP_END();
>> -}
>> -
>> void optc3_set_odm_bypass(struct timing_generator *optc,
>> const struct dc_crtc_timing *dc_crtc_timing)
>> {
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
>> index 33bd12f5dc17..dd45a5499b07 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
>> @@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
>>
>> void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
>>
>> -void optc3_set_vrr_m_const(struct timing_generator *optc,
>> - double vtotal_avg);
>> -
>> void optc3_set_drr_trigger_window(struct timing_generator *optc,
>> uint32_t window_start, uint32_t window_end);
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
>> index 9861be1dc063..1fad7b48bd5b 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
>> @@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
>> .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
>> .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
>> .enable_optc_clock = optc1_enable_optc_clock,
>> - .set_vrr_m_const = optc3_set_vrr_m_const,
>> .set_drr = optc32_set_drr,
>> .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
>> .set_vtotal_min_max = optc3_set_vtotal_min_max,
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> index e1e92daba668..814374b1016c 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
>> @@ -177,83 +177,6 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
>> .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
>> };
>>
>> -
>> -void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
>> - double vtotal_avg)
>> -{
>> - struct optc *optc1 = DCN10TG_FROM_TG(optc);
>> - double vtotal_min, vtotal_max;
>> - double ratio, modulo, phase;
>> - uint32_t vblank_start;
>> - uint32_t v_total_mask_value = 0;
>> -
>> - dc_assert_fp_enabled();
>> -
>> - /* Compute VTOTAL_MIN and VTOTAL_MAX, so that
>> - * VOTAL_MAX - VTOTAL_MIN = 1
>> - */
>> - v_total_mask_value = 16;
>> - vtotal_min = dcn_bw_floor(vtotal_avg);
>> - vtotal_max = dcn_bw_ceil(vtotal_avg);
>> -
>> - /* Check that bottom VBLANK is at least 2 lines tall when running with
>> - * VTOTAL_MIN. Note that VTOTAL registers are defined as 'total number
>> - * of lines in a frame - 1'.
>> - */
>> - REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START,
>> - &vblank_start);
>> - ASSERT(vtotal_min >= vblank_start + 1);
>> -
>> - /* Special case where the average frame rate can be achieved
>> - * without using the DTO
>> - */
>> - if (vtotal_min == vtotal_max) {
>> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);
>> -
>> - optc->funcs->set_vtotal_min_max(optc, 0, 0);
>> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);
>> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);
>> - REG_UPDATE_3(OTG_V_TOTAL_CONTROL,
>> - OTG_V_TOTAL_MIN_SEL, 0,
>> - OTG_V_TOTAL_MAX_SEL, 0,
>> - OTG_SET_V_TOTAL_MIN_MASK_EN, 0);
>> - return;
>> - }
>> -
>> - ratio = vtotal_max - vtotal_avg;
>> - modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */
>> - phase = ratio * modulo;
>> -
>> - /* Special cases where the DTO phase gets rounded to 0 or
>> - * to DTO modulo
>> - */
>> - if (phase <= 0 || phase >= modulo) {
>> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL,
>> - phase <= 0 ?
>> - (uint32_t)vtotal_max : (uint32_t)vtotal_min);
>> - REG_SET(OTG_V_TOTAL_MIN, 0, OTG_V_TOTAL_MIN, 0);
>> - REG_SET(OTG_V_TOTAL_MAX, 0, OTG_V_TOTAL_MAX, 0);
>> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);
>> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);
>> - REG_UPDATE_3(OTG_V_TOTAL_CONTROL,
>> - OTG_V_TOTAL_MIN_SEL, 0,
>> - OTG_V_TOTAL_MAX_SEL, 0,
>> - OTG_SET_V_TOTAL_MIN_MASK_EN, 0);
>> - return;
>> - }
>> - REG_UPDATE_6(OTG_V_TOTAL_CONTROL,
>> - OTG_V_TOTAL_MIN_SEL, 1,
>> - OTG_V_TOTAL_MAX_SEL, 1,
>> - OTG_SET_V_TOTAL_MIN_MASK_EN, 1,
>> - OTG_SET_V_TOTAL_MIN_MASK, v_total_mask_value,
>> - OTG_VTOTAL_MID_REPLACING_MIN_EN, 0,
>> - OTG_VTOTAL_MID_REPLACING_MAX_EN, 0);
>> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);
>> - optc->funcs->set_vtotal_min_max(optc, vtotal_min, vtotal_max);
>> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase);
>> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, (uint32_t)modulo);
>> -}
>> -
>> void dcn30_fpu_populate_dml_writeback_from_context(
>> struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
>> {
>> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
>> index cab864095ce7..e3b6ad6a8784 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
>> @@ -29,9 +29,6 @@
>> #include "core_types.h"
>> #include "dcn20/dcn20_optc.h"
>>
>> -void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
>> - double vtotal_avg);
>> -
>> void dcn30_fpu_populate_dml_writeback_from_context(
>> struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
>>
>> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
>> index 828e5c6ad1cf..72eef7a5ed83 100644
>> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
>> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
>> @@ -310,8 +310,6 @@ struct timing_generator_funcs {
>> int group_idx,
>> uint32_t gsl_ready_signal);
>> void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
>> - void (*set_vrr_m_const)(struct timing_generator *optc,
>> - double vtotal_avg);
>> void (*set_drr_trigger_window)(struct timing_generator *optc,
>> uint32_t window_start, uint32_t window_end);
>> void (*set_vtotal_change_limit)(struct timing_generator *optc,
>> --
>> 2.35.1
>>
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