[PATCH 2/2] drm/amdgpu: Init VF's HDP flush reg offset early
Alex Deucher
alexdeucher at gmail.com
Thu Aug 25 13:22:15 UTC 2022
Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
On Thu, Aug 25, 2022 at 4:58 AM Lijo Lazar <lijo.lazar at amd.com> wrote:
>
> Make sure the register offsets used for HDP flush in VF is
> initialized early so that it works fine during any early HDP flush
> sequence. For that, move the offset initialization to *_remap_hdp.
>
> Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 23 +++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 12 +++++++----
> drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 23 +++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c | 21 ++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 24 ++++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 23 +++++++++++++--------
> 7 files changed, 84 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 53d753e94a71..c0bb2e9616c5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -2382,7 +2382,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
> * to process space. This is needed for any early HDP
> * flush operation during gmc initialization.
> */
> - if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
> + if (adev->nbio.funcs->remap_hdp_registers)
> adev->nbio.funcs->remap_hdp_registers(adev);
>
> r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> index b465baa26762..20fa2c5ad510 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
> @@ -65,10 +65,21 @@
>
> static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (amdgpu_sriov_vf(adev))
> + adev->rmmio_remap.reg_offset =
> + SOC15_REG_OFFSET(
> + NBIO, 0,
> + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
> + << 2;
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v2_3_get_rev_id(struct amdgpu_device *adev)
> @@ -338,10 +349,6 @@ static void nbio_v2_3_init_registers(struct amdgpu_device *adev)
>
> if (def != data)
> WREG32_PCIE(smnPCIE_CONFIG_CNTL, data);
> -
> - if (amdgpu_sriov_vf(adev))
> - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
> - mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> }
>
> #define NAVI10_PCIE__LC_L0S_INACTIVITY_DEFAULT 0x00000000 // off by default, no gains over L1
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> index 982a89f841d5..e011d9856794 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c
> @@ -30,10 +30,14 @@
>
> static void nbio_v4_3_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v4_3_get_rev_id(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> index f7f6ddebd3e4..7536ca3fcd69 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c
> @@ -55,10 +55,21 @@
>
> static void nbio_v6_1_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (amdgpu_sriov_vf(adev))
> + adev->rmmio_remap.reg_offset =
> + SOC15_REG_OFFSET(
> + NBIO, 0,
> + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
> + << 2;
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
> @@ -276,10 +287,6 @@ static void nbio_v6_1_init_registers(struct amdgpu_device *adev)
>
> if (def != data)
> WREG32_PCIE(smnPCIE_CI_CNTL, data);
> -
> - if (amdgpu_sriov_vf(adev))
> - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
> - mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> }
>
> static void nbio_v6_1_program_ltr(struct amdgpu_device *adev)
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> index aa0326d00c72..6b4ac16a8466 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_0.c
> @@ -35,10 +35,20 @@
>
> static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (amdgpu_sriov_vf(adev))
> + adev->rmmio_remap.reg_offset =
> + SOC15_REG_OFFSET(NBIO, 0,
> + mmHDP_MEM_COHERENCY_FLUSH_CNTL)
> + << 2;
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
> @@ -273,9 +283,6 @@ const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
>
> static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
> {
> - if (amdgpu_sriov_vf(adev))
> - adev->rmmio_remap.reg_offset =
> - SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> }
>
> const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 31776b12e4c4..fb4be72eade7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -49,10 +49,21 @@
>
> static void nbio_v7_2_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (amdgpu_sriov_vf(adev))
> + adev->rmmio_remap.reg_offset =
> + SOC15_REG_OFFSET(
> + NBIO, 0,
> + regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
> + << 2;
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v7_2_get_rev_id(struct amdgpu_device *adev)
> @@ -369,6 +380,7 @@ const struct nbio_hdp_flush_reg nbio_v7_2_hdp_flush_reg = {
> static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
> {
> uint32_t def, data;
> +
> switch (adev->ip_versions[NBIO_HWIP][0]) {
> case IP_VERSION(7, 2, 1):
> case IP_VERSION(7, 3, 0):
> @@ -393,10 +405,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
> WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL), data);
> break;
> }
> -
> - if (amdgpu_sriov_vf(adev))
> - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
> - regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> }
>
> const struct amdgpu_nbio_funcs nbio_v7_2_funcs = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> index 11848d1e238b..3c11af99582f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c
> @@ -101,10 +101,21 @@ static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
>
> static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
> {
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> - WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> - adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + if (amdgpu_sriov_vf(adev))
> + adev->rmmio_remap.reg_offset =
> + SOC15_REG_OFFSET(
> + NBIO, 0,
> + mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL)
> + << 2;
> +
> + if (!amdgpu_sriov_vf(adev)) {
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
> + WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
> + adev->rmmio_remap.reg_offset +
> + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
> + }
> }
>
> static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
> @@ -343,10 +354,6 @@ static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
> {
> uint32_t baco_cntl;
>
> - if (amdgpu_sriov_vf(adev))
> - adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
> - mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> -
> if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(7, 4, 4) &&
> !amdgpu_sriov_vf(adev)) {
> baco_cntl = RREG32_SOC15(NBIO, 0, mmBACO_CNTL);
> --
> 2.25.1
>
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