[PATCH 1/7] drm/amdgpu/gmc9: don't touch gfxhub registers during S0ix

[Alex Deucher]

On Thu, Dec 15, 2022 at 2:45 AM Christian König
<ckoenig.leichtzumerken at gmail.com> wrote:
>
> Am 14.12.22 um 23:16 schrieb Alex Deucher:
> > gfxhub registers are part of gfx IP and should not need to be
> > changed.  Doing so without disabling gfxoff can hang the gfx IP.
> >
> > Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 26 ++++++++++++++++++++------
> >   1 file changed, 20 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > index 08d6cf79fb15..5f07c85bf729 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> > @@ -484,6 +484,9 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> >                       for (i = 0; i < 16; i++) {
> >                               reg = hub->vm_context0_cntl + i;
> >
> > +                             if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
> > +                                     continue;
> > +
>
> I'm not sure we can do this because the higher layer will then have an
> incorrect impression of the interrupt state here.

In this particular case it works because we only touch this interrupt
on init/resume and fini/suspend.  So over the course of a s0i3 cycle
the state would end up being the same, we just don't touch the
registers.

Alex

>
> Christian.
>
> >                               if (j == AMDGPU_GFXHUB_0)
> >                                       tmp = RREG32_SOC15_IP(GC, reg);
> >                               else
> > @@ -504,6 +507,9 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
> >                       for (i = 0; i < 16; i++) {
> >                               reg = hub->vm_context0_cntl + i;
> >
> > +                             if (adev->in_s0ix && (j == AMDGPU_GFXHUB_0))
> > +                                     continue;
> > +
> >                               if (j == AMDGPU_GFXHUB_0)
> >                                       tmp = RREG32_SOC15_IP(GC, reg);
> >                               else
> > @@ -1862,9 +1868,12 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
> >       }
> >
> >       amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
> > -     r = adev->gfxhub.funcs->gart_enable(adev);
> > -     if (r)
> > -             return r;
> > +
> > +     if (!adev->in_s0ix) {
> > +             r = adev->gfxhub.funcs->gart_enable(adev);
> > +             if (r)
> > +                     return r;
> > +     }
> >
> >       r = adev->mmhub.funcs->gart_enable(adev);
> >       if (r)
> > @@ -1911,11 +1920,15 @@ static int gmc_v9_0_hw_init(void *handle)
> >               value = true;
> >
> >       if (!amdgpu_sriov_vf(adev)) {
> > -             adev->gfxhub.funcs->set_fault_enable_default(adev, value);
> > +             if (!adev->in_s0ix)
> > +                     adev->gfxhub.funcs->set_fault_enable_default(adev, value);
> >               adev->mmhub.funcs->set_fault_enable_default(adev, value);
> >       }
> > -     for (i = 0; i < adev->num_vmhubs; ++i)
> > +     for (i = 0; i < adev->num_vmhubs; ++i) {
> > +             if (adev->in_s0ix && (i == AMDGPU_GFXHUB_0))
> > +                     continue;
> >               gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
> > +     }
> >
> >       if (adev->umc.funcs && adev->umc.funcs->init_registers)
> >               adev->umc.funcs->init_registers(adev);
> > @@ -1939,7 +1952,8 @@ static int gmc_v9_0_hw_init(void *handle)
> >    */
> >   static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
> >   {
> > -     adev->gfxhub.funcs->gart_disable(adev);
> > +     if (!adev->in_s0ix)
> > +             adev->gfxhub.funcs->gart_disable(adev);
> >       adev->mmhub.funcs->gart_disable(adev);
> >   }
> >
>