[PATCH] drm/amd/display: Cap pflip irqs per max otg number

[Kazlauskas, Nicholas]

On 2/3/2022 5:14 PM, Roman.Li at amd.com wrote:
> From: Roman Li <Roman.Li at amd.com>
> 
> [Why]
> pflip interrupt order are mapped 1 to 1 to otg id.
> e.g. if irq_src=26 corresponds to otg0 then 27->otg1, 28->otg2...
> 
> Linux DM registers pflip interrupts per number of crtcs.
> In fused pipe case crtc numbers can be less than otg id.
> 
> e.g. if one pipe out of 3(otg#0-2) is fused adev->mode_info.num_crtc=2
> so DM only registers irq_src 26,27.
> This is a bug since if pipe#2 remains unfused DM never gets
> otg2 pflip interrupt (irq_src=28)
> That may results in gfx failure due to pflip timeout.
> 
> [How]
> Register pflip interrupts per max num of otg instead of num_crtc
> 
> Signed-off-by: Roman Li <Roman.Li at amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>

Regards,
Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>   drivers/gpu/drm/amd/display/dc/core/dc.c          | 2 ++
>   drivers/gpu/drm/amd/display/dc/dc.h               | 1 +
>   3 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 8f53c9f..10ca3fc 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -3646,7 +3646,7 @@ static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
>   
>   	/* Use GRPH_PFLIP interrupt */
>   	for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
> -			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
> +			i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + dc->caps.max_otg_num - 1;
>   			i++) {
>   		r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
>   		if (r) {
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
> index 1d9404f..70a0b89 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
> @@ -1220,6 +1220,8 @@ struct dc *dc_create(const struct dc_init_data *init_params)
>   
>   		dc->caps.max_dp_protocol_version = DP_VERSION_1_4;
>   
> +		dc->caps.max_otg_num = dc->res_pool->res_cap->num_timing_generator;
> +
>   		if (dc->res_pool->dmcu != NULL)
>   			dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version;
>   	}
> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
> index 69d264d..af05877 100644
> --- a/drivers/gpu/drm/amd/display/dc/dc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
> @@ -200,6 +200,7 @@ struct dc_caps {
>   	bool edp_dsc_support;
>   	bool vbios_lttpr_aware;
>   	bool vbios_lttpr_enable;
> +	uint32_t max_otg_num;
>   };
>   
>   struct dc_bug_wa {