[PATCH] drm/amdgpu: no rlcg legacy read in SRIOV case

[Skvortsov, Victor]

[AMD Official Use Only]

Reviewed-by: Victor Skvortsov <Victor.Skvortsov at amd.com>

Thanks,
Victor

-----Original Message-----
From: Zhang, Hawking <Hawking.Zhang at amd.com> 
Sent: Friday, February 11, 2022 1:42 AM
To: Chen, Guchun <Guchun.Chen at amd.com>; amd-gfx at lists.freedesktop.org; Zhou, Peng Ju <PengJu.Zhou at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Skvortsov, Victor <Victor.Skvortsov at amd.com>
Subject: RE: [PATCH] drm/amdgpu: no rlcg legacy read in SRIOV case

[AMD Official Use Only]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking

-----Original Message-----
From: Chen, Guchun <Guchun.Chen at amd.com> 
Sent: Friday, February 11, 2022 13:39
To: amd-gfx at lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang at amd.com>; Zhou, Peng Ju <PengJu.Zhou at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Skvortsov, Victor <Victor.Skvortsov at amd.com>
Cc: Chen, Guchun <Guchun.Chen at amd.com>
Subject: [PATCH] drm/amdgpu: no rlcg legacy read in SRIOV case

rlcg legacy read is not available in SRIOV configration.
Otherwise, gmc_v9_0_flush_gpu_tlb will always complain timeout and finally breaks driver load.

v2: bypass read in amdgpu_virt_get_rlcg_reg_access_flag (from Victor)

Fixes: 0dc4a7e75581("drm/amdgpu: switch to get_rlcg_reg_access_flag for gfx9")
Signed-off-by: Guchun Chen <guchun.chen at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index e1288901beb6..6668d7fa89e4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -836,7 +836,7 @@ static bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev,
 		/* only in new version, AMDGPU_REGS_NO_KIQ and
 		 * AMDGPU_REGS_RLC are enabled simultaneously */
 		} else if ((acc_flags & AMDGPU_REGS_RLC) &&
-			   !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
+				!(acc_flags & AMDGPU_REGS_NO_KIQ) && write) {
 			*rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
 			ret = true;
 		}
@@ -940,7 +940,7 @@ void amdgpu_sriov_wreg(struct amdgpu_device *adev,
 	u32 rlcg_flag;
 
 	if (!amdgpu_sriov_runtime(adev) &&
-	    amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, &rlcg_flag)) {
+		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, true, 
+&rlcg_flag)) {
 		amdgpu_virt_rlcg_reg_rw(adev, offset, value, rlcg_flag);
 		return;
 	}
@@ -957,7 +957,7 @@ u32 amdgpu_sriov_rreg(struct amdgpu_device *adev,
 	u32 rlcg_flag;
 
 	if (!amdgpu_sriov_runtime(adev) &&
-	    amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, &rlcg_flag))
+		amdgpu_virt_get_rlcg_reg_access_flag(adev, acc_flags, hwip, false, 
+&rlcg_flag))
 		return amdgpu_virt_rlcg_reg_rw(adev, offset, 0, rlcg_flag);
 
 	if (acc_flags & AMDGPU_REGS_NO_KIQ)
--
2.17.1