[PATCH 00/13] Update DCN 3.1 support for 3.1.5

Alex Deucher alexander.deucher at amd.com
Fri Feb 18 16:58:43 UTC 2022


Update DCN 3.1 for 3.1.5.  This is a minor update
to DCN 3.1 display support in amdgpu.

The first two patches are register headers so I did not
send them out due to size.

Qingqing Zhuo (11):
  drm/amd/include: add DCN 3.1.5 registers
  drm/amd/display: Add DCN315 family information
  drm/amd/display: Add DCN315 CLK_MGR
  drm/amd/display: Add DCN315 GPIO
  drm/amd/display: Add DCN315 IRQ
  drm/amd/display: Add DCN315 DMUB
  drm/amd/display: Add DCN315 Resource
  drm/amd/display: Add DCN315 Command Table Helper
  drm/amd/display: Add DCN315 blocks to Makefile
  drm/amd/display: Add DCN315 CORE
  drm/amd/display: Add DCN315 DM Support

Yifan Zhang (2):
  drm/amdgpu: add mp 13.0.5 header files
  drm/amdgpu: add dm ip block for dcn 3.1.5

 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c |      1 +
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |     14 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    |      1 +
 drivers/gpu/drm/amd/display/dc/Makefile       |      1 +
 .../display/dc/bios/command_table_helper2.c   |      1 +
 .../gpu/drm/amd/display/dc/clk_mgr/Makefile   |      9 +
 .../gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c  |     23 +-
 .../dc/clk_mgr/dcn315/dcn315_clk_mgr.c        |    607 +
 .../dc/clk_mgr/dcn315/dcn315_clk_mgr.h        |     49 +
 .../display/dc/clk_mgr/dcn315/dcn315_smu.c    |    329 +
 .../display/dc/clk_mgr/dcn315/dcn315_smu.h    |    126 +
 drivers/gpu/drm/amd/display/dc/core/dc_link.c |     13 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |      8 +
 .../gpu/drm/amd/display/dc/dcn315/Makefile    |     56 +
 .../amd/display/dc/dcn315/dcn315_resource.c   |   2302 +
 .../amd/display/dc/dcn315/dcn315_resource.h   |     42 +
 drivers/gpu/drm/amd/display/dc/gpio/Makefile  |      8 +
 .../dc/gpio/dcn315/hw_factory_dcn315.c        |    260 +
 .../dc/gpio/dcn315/hw_factory_dcn315.h        |     31 +
 .../dc/gpio/dcn315/hw_translate_dcn315.c      |    374 +
 .../dc/gpio/dcn315/hw_translate_dcn315.h      |     33 +
 .../gpu/drm/amd/display/dc/gpio/hw_factory.c  |      4 +
 .../drm/amd/display/dc/gpio/hw_translate.c    |      4 +
 drivers/gpu/drm/amd/display/dc/irq/Makefile   |      8 +
 .../dc/irq/dcn315/irq_service_dcn315.c        |    438 +
 .../dc/irq/dcn315/irq_service_dcn315.h        |     34 +
 drivers/gpu/drm/amd/display/dmub/dmub_srv.h   |      1 +
 drivers/gpu/drm/amd/display/dmub/src/Makefile |      4 +-
 .../drm/amd/display/dmub/src/dmub_dcn315.c    |     62 +
 .../drm/amd/display/dmub/src/dmub_dcn315.h    |     68 +
 .../gpu/drm/amd/display/dmub/src/dmub_srv.c   |      9 +-
 .../gpu/drm/amd/display/include/dal_asic_id.h |      6 +
 .../gpu/drm/amd/display/include/dal_types.h   |      1 +
 .../include/asic_reg/dcn/dcn_3_1_5_offset.h   |  15191 +++
 .../include/asic_reg/dcn/dcn_3_1_5_sh_mask.h  |  62061 +++++++++
 .../include/asic_reg/dpcs/dpcs_4_2_2_offset.h |  11957 ++
 .../asic_reg/dpcs/dpcs_4_2_2_sh_mask.h        | 103633 +++++++++++++++
 .../include/asic_reg/mp/mp_13_0_5_offset.h    |    455 +
 .../include/asic_reg/mp/mp_13_0_5_sh_mask.h   |    672 +
 39 files changed, 198885 insertions(+), 11 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_smu.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn315/Makefile
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_factory_dcn315.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/gpio/dcn315/hw_translate_dcn315.h
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.c
 create mode 100644 drivers/gpu/drm/amd/display/dc/irq/dcn315/irq_service_dcn315.h
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.c
 create mode 100644 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn315.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_1_5_sh_mask.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/dpcs/dpcs_4_2_2_sh_mask.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_offset.h
 create mode 100644 drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_5_sh_mask.h

-- 
2.35.1



More information about the amd-gfx mailing list