[bug report] drm/amdgpu: Modify gfx block to fit for the unified ras block data and ops

Dan Carpenter dan.carpenter at oracle.com
Thu Jan 13 06:16:11 UTC 2022


Hello yipechai,

The patch d51ce4db0747: "drm/amdgpu: Modify gfx block to fit for the
unified ras block data and ops" from Jan 4, 2022, leads to the
following Smatch static checker warning:

	drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:1058 amdgpu_ras_error_inject()
	warn: inconsistent indenting

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
    1047 int amdgpu_ras_error_inject(struct amdgpu_device *adev,
    1048                 struct ras_inject_if *info)
    1049 {
    1050         struct ras_manager *obj = amdgpu_ras_find_obj(adev, &info->head);
    1051         struct ta_ras_trigger_error_input block_info = {
    1052                 .block_id =  amdgpu_ras_block_to_ta(info->head.block),
    1053                 .inject_error_type = amdgpu_ras_error_to_ta(info->head.type),
    1054                 .sub_block_index = info->head.sub_block_index,
    1055                 .address = info->address,
    1056                 .value = info->value,
    1057         };
--> 1058     int ret = -EINVAL;
    1059     struct amdgpu_ras_block_object* block_obj = amdgpu_ras_get_ras_block(adev, info->head.block, info->head.sub_block_index);

Really?  You can't be bothered to run checkpatch on your code?  AMD drm
code is uniquely bad in this regards.  It's the only place outside of
drivers/staging/ where you see stuff like this.

In theory, it's admirable to be this informal and free from bureaucracy
and rules.  But in another way, this kind of code is like plumber crack.
You might be a good plumber but it's not attractive.  And we might not
point it out, but we all see it.

    1060 
    1061         if (!obj)
    1062                 return -EINVAL;
    1063 
    1064         if (!block_obj || !block_obj->hw_ops)        {
    1065                 dev_info(adev->dev, "%s doesn't config ras function \n", get_ras_block_str(&info->head));
    1066                 return -EINVAL;
    1067         }

regards,
dan carpenter


More information about the amd-gfx mailing list