[PATCH] drm/amd/display: Shorten delay time to 1us while resetting FIFO

[Liu, Zhan]

[Public]

Thank you all for the review. I've found a better solution here, so I will retire this patch, and re-submit a different one.

Thanks,
Zhan

> -----Original Message-----
> From: Liu, Zhan <Zhan.Liu at amd.com>
> Sent: 2022/January/19, Wednesday 5:24 PM
> To: Liu, Zhan <Zhan.Liu at amd.com>; amd-gfx at lists.freedesktop.org
> Cc: Liu, Charlene <Charlene.Liu at amd.com>; Kotarac, Pavle
> <Pavle.Kotarac at amd.com>; Pierre-Loup Griffais <pgriffais at valvesoftware.com>;
> Gutierrez, Agustin <Agustin.Gutierrez at amd.com>; Cornij, Nikola
> <Nikola.Cornij at amd.com>
> Subject: RE: [PATCH] drm/amd/display: Shorten delay time to 1us while resetting
> FIFO
>
> [Public]
>
> Apologize for sending out the patch with the wrong sensitivity a few seconds ago.
> I've updated sensitivity policy to "Public" here.
>
> Thanks,
> Zhan
>
> > -----Original Message-----
> > From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of
> > Liu, Zhan
> > Sent: 2022/January/19, Wednesday 5:19 PM
> > To: amd-gfx at lists.freedesktop.org
> > Cc: Liu, Charlene <Charlene.Liu at amd.com>; Kotarac, Pavle
> > <Pavle.Kotarac at amd.com>; Pierre-Loup Griffais
> > <pgriffais at valvesoftware.com>; Gutierrez, Agustin
> > <Agustin.Gutierrez at amd.com>; Cornij, Nikola <Nikola.Cornij at amd.com>
> > Subject: [PATCH] drm/amd/display: Shorten delay time to 1us while
> > resetting FIFO
> >
> > [Why]
> > Current FIFO reset delay for dcn10 is 100us, which is too long and
> > will fail atomic flip. As a result, there will be no display on boot.
> >
> > [How]
> > Shorten delay time to 1us. This also aligns with FIFO reset delay on other ASICs.
> >
> > Signed-off-by: Zhan Liu <zhan.liu at amd.com>
> > ---
> >  drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git
> > a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > index bf4436d7aaab..2077c22befa5 100644
> > --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c
> > @@ -909,7 +909,7 @@ void enc1_stream_encoder_reset_fifo(
> >
> >         /* set DIG_START to 0x1 to reset FIFO */
> >         REG_UPDATE(DIG_FE_CNTL, DIG_START, 1);
> > -       udelay(100);
> > +       udelay(1);
> >
> >         /* write 0 to take the FIFO out of reset */
> >         REG_UPDATE(DIG_FE_CNTL, DIG_START, 0);
> > --
> > 2.25.1