[PATCH 1/9] drm/amdgpu: add helper to query rlcg reg access flag

[Lazar, Lijo]

Series is
	Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>

Thanks,
Lijo

On 1/20/2022 4:48 PM, Hawking Zhang wrote:
> Query rlc indirect register access approach specified
> by sriov host driver per ip blocks
> 
> Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com>
> Reviewed-by: Zhou, Peng Ju <PengJu.Zhou at amd.com>
> Acked-by: Christian König <christian.koenig at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 35 ++++++++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  8 ++++++
>   2 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index 07bc0f504713..a40e4fcdfa46 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -820,3 +820,38 @@ void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
>   		}
>   	}
>   }
> +
> +bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags,
> +					  u32 hwip, bool write, u32 *rlcg_flag)
> +{
> +	bool ret = false;
> +
> +	switch (hwip) {
> +	case GC_HWIP:
> +		if (amdgpu_sriov_reg_indirect_gc(adev)) {
> +			*rlcg_flag =
> +				write ? AMDGPU_RLCG_GC_WRITE : AMDGPU_RLCG_GC_READ;
> +			ret = true;
> +		/* only in new version, AMDGPU_REGS_NO_KIQ and
> +		 * AMDGPU_REGS_RLC are enabled simultaneously */
> +		} else if ((acc_flags & AMDGPU_REGS_RLC) &&
> +			   !(acc_flags & AMDGPU_REGS_NO_KIQ)) {
> +			*rlcg_flag = AMDGPU_RLCG_GC_WRITE_LEGACY;
> +			ret = true;
> +		}
> +		break;
> +	case MMHUB_HWIP:
> +		if (amdgpu_sriov_reg_indirect_mmhub(adev) &&
> +		    (acc_flags & AMDGPU_REGS_RLC) && write) {
> +			*rlcg_flag = AMDGPU_RLCG_MMHUB_WRITE;
> +			ret = true;
> +		}
> +		break;
> +	default:
> +		dev_err(adev->dev,
> +			"indirect registers access through rlcg is not supported\n");
> +		ret = false;
> +		break;
> +	}
> +	return ret;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 9adfb8d63280..404a06e57f30 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -32,6 +32,12 @@
>   #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
>   #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
>   
> +/* flags for indirect register access path supported by rlcg for sriov */
> +#define AMDGPU_RLCG_GC_WRITE_LEGACY    (0x8 << 28)
> +#define AMDGPU_RLCG_GC_WRITE           (0x0 << 28)
> +#define AMDGPU_RLCG_GC_READ            (0x1 << 28)
> +#define AMDGPU_RLCG_MMHUB_WRITE        (0x2 << 28)
> +
>   /* all asic after AI use this offset */
>   #define mmRCC_IOV_FUNC_IDENTIFIER 0xDE5
>   /* tonga/fiji use this offset */
> @@ -321,4 +327,6 @@ enum amdgpu_sriov_vf_mode amdgpu_virt_get_sriov_vf_mode(struct amdgpu_device *ad
>   void amdgpu_virt_update_sriov_video_codec(struct amdgpu_device *adev,
>   			struct amdgpu_video_codec_info *encode, uint32_t encode_array_size,
>   			struct amdgpu_video_codec_info *decode, uint32_t decode_array_size);
> +bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags,
> +					  u32 hwip, bool write, u32 *rlcg_flag);
>   #endif
>