[PATCH 2/2] drm/amd/display: Wrap dcn301_calculate_wm_and_dlg for FPU.

[Alex Deucher]

Applied the series.  Thanks!

Alex

On Sun, Jan 23, 2022 at 7:23 PM Bas Nieuwenhuizen
<bas at basnieuwenhuizen.nl> wrote:
>
> Mirrors the logic for dcn30. Cue lots of WARNs and some
> kernel panics without this fix.
>
> Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
> ---
>  .../gpu/drm/amd/display/dc/dcn301/dcn301_resource.c   | 11 +++++++++++
>  .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c    |  2 +-
>  .../gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h    |  2 +-
>  3 files changed, 13 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> index b4001233867c..5d9637b07429 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
> @@ -1380,6 +1380,17 @@ static void set_wm_ranges(
>         pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
>  }
>
> +static void dcn301_calculate_wm_and_dlg(
> +               struct dc *dc, struct dc_state *context,
> +               display_e2e_pipe_params_st *pipes,
> +               int pipe_cnt,
> +               int vlevel)
> +{
> +       DC_FP_START();
> +       dcn301_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
> +       DC_FP_END();
> +}
> +
>  static struct resource_funcs dcn301_res_pool_funcs = {
>         .destroy = dcn301_destroy_resource_pool,
>         .link_enc_create = dcn301_link_encoder_create,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> index 94c32832a0e7..0a7a33864973 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.c
> @@ -327,7 +327,7 @@ void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
>                 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
>  }
>
> -void dcn301_calculate_wm_and_dlg(struct dc *dc,
> +void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
>                 struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
>                 int pipe_cnt,
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
> index fc7065d17842..774b0fdfc80b 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn301/dcn301_fpu.h
> @@ -34,7 +34,7 @@ void dcn301_fpu_set_wm_ranges(int i,
>
>  void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info);
>
> -void dcn301_calculate_wm_and_dlg(struct dc *dc,
> +void dcn301_calculate_wm_and_dlg_fp(struct dc *dc,
>                 struct dc_state *context,
>                 display_e2e_pipe_params_st *pipes,
>                 int pipe_cnt,
> --
> 2.34.1
>