[PATCH 10/17] drm/amd/display: add set dp lane settings to link_hwss
Stylon Wang
stylon.wang at amd.com
Fri Jan 28 14:04:04 UTC 2022
From: Wenjing Liu <wenjing.liu at amd.com>
[why]
Factor set dp lane settings to link_hwss.
Reviewed-by: Jun Lei <Jun.Lei at amd.com>
Acked-by: Stylon Wang <stylon.wang at amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu at amd.com>
---
.../drm/amd/display/dc/core/dc_link_hwss.c | 40 ++++++++++++++-----
.../drm/amd/display/dc/dce/dce_link_encoder.c | 17 ++++----
.../drm/amd/display/dc/dce/dce_link_encoder.h | 3 +-
.../amd/display/dc/dcn10/dcn10_link_encoder.c | 17 ++++----
.../amd/display/dc/dcn10/dcn10_link_encoder.h | 3 +-
.../drm/amd/display/dc/inc/hw/link_encoder.h | 3 +-
.../gpu/drm/amd/display/dc/inc/link_hwss.h | 4 ++
.../display/dc/virtual/virtual_link_encoder.c | 3 +-
8 files changed, 59 insertions(+), 31 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
index d5670d3b1a4b..3b7ab2ca34c6 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
@@ -295,22 +295,16 @@ void dp_set_hw_lane_settings(
const struct link_training_settings *link_settings,
uint32_t offset)
{
- struct link_encoder *encoder = link->link_enc;
+ const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && !is_immediate_downstream(link, offset))
return;
- /* call Encoder to set lane settings */
- if (dp_get_link_encoding_format(&link_settings->link_settings) ==
- DP_128b_132b_ENCODING) {
- link_res->hpo_dp_link_enc->funcs->set_ffe(
- link_res->hpo_dp_link_enc,
+ if (link_hwss->ext.set_dp_lane_settings)
+ link_hwss->ext.set_dp_lane_settings(link, link_res,
&link_settings->link_settings,
- link_settings->lane_settings[0].FFE_PRESET.raw);
- } else if (dp_get_link_encoding_format(&link_settings->link_settings)
- == DP_8b_10b_ENCODING) {
- encoder->funcs->dp_set_lane_settings(encoder, link_settings);
- }
+ link_settings->hw_lane_settings);
+
memmove(link->cur_lane_setting,
link_settings->lane_settings,
sizeof(link->cur_lane_setting));
@@ -748,6 +742,16 @@ static void set_dio_dp_link_test_pattern(struct dc_link *link,
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
}
+static void set_dio_dp_lane_settings(struct dc_link *link,
+ const struct link_resource *link_res,
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
+{
+ struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
+
+ link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings);
+}
+
static const struct link_hwss dio_link_hwss = {
.setup_stream_encoder = setup_dio_stream_encoder,
.reset_stream_encoder = reset_dio_stream_encoder,
@@ -756,6 +760,7 @@ static const struct link_hwss dio_link_hwss = {
.enable_dp_link_output = enable_dio_dp_link_output,
.disable_dp_link_output = disable_dio_dp_link_output,
.set_dp_link_test_pattern = set_dio_dp_link_test_pattern,
+ .set_dp_lane_settings = set_dio_dp_lane_settings,
},
};
@@ -931,6 +936,17 @@ static void set_hpo_dp_link_test_pattern(struct dc_link *link,
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
}
+static void set_hpo_dp_lane_settings(struct dc_link *link,
+ const struct link_resource *link_res,
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
+{
+ link_res->hpo_dp_link_enc->funcs->set_ffe(
+ link_res->hpo_dp_link_enc,
+ link_settings,
+ lane_settings[0].FFE_PRESET.raw);
+}
+
static const struct link_hwss hpo_dp_link_hwss = {
.setup_stream_encoder = setup_hpo_dp_stream_encoder,
.reset_stream_encoder = reset_hpo_dp_stream_encoder,
@@ -940,6 +956,7 @@ static const struct link_hwss hpo_dp_link_hwss = {
.enable_dp_link_output = enable_hpo_dp_link_output,
.disable_dp_link_output = disable_hpo_dp_link_output,
.set_dp_link_test_pattern = set_hpo_dp_link_test_pattern,
+ .set_dp_lane_settings = set_hpo_dp_lane_settings,
},
};
/*********************** below goes to dpia_link_hwss *************************/
@@ -958,6 +975,7 @@ static const struct link_hwss dpia_link_hwss = {
.enable_dp_link_output = enable_dio_dp_link_output,
.disable_dp_link_output = disable_dio_dp_link_output,
.set_dp_link_test_pattern = set_dio_dp_link_test_pattern,
+ .set_dp_lane_settings = set_dio_dp_lane_settings,
},
};
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
index f1c61d5aee6c..0bc41414481e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
@@ -1325,7 +1325,8 @@ void dce110_link_encoder_disable_output(
void dce110_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
- const struct link_training_settings *link_settings)
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
union dpcd_training_lane_set training_lane_set = { { 0 } };
@@ -1340,26 +1341,26 @@ void dce110_link_encoder_dp_set_lane_settings(
cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl.transmitter = enc110->base.transmitter;
cntl.connector_obj_id = enc110->base.connector;
- cntl.lanes_number = link_settings->link_settings.lane_count;
+ cntl.lanes_number = link_settings->lane_count;
cntl.hpd_sel = enc110->base.hpd_source;
- cntl.pixel_clock = link_settings->link_settings.link_rate *
+ cntl.pixel_clock = link_settings->link_rate *
LINK_RATE_REF_FREQ_IN_KHZ;
- for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
+ for (lane = 0; lane < link_settings->lane_count; lane++) {
/* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET =
- link_settings->lane_settings[lane].VOLTAGE_SWING;
+ lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET =
- link_settings->lane_settings[lane].PRE_EMPHASIS;
+ lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */
- if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
+ if (link_settings->link_rate == LINK_RATE_HIGH2) {
/* this is passed to VBIOS
* to program post cursor 2 level */
training_lane_set.bits.POST_CURSOR2_SET =
- link_settings->lane_settings[lane].POST_CURSOR2;
+ lane_settings[lane].POST_CURSOR2;
}
cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
index fc6ade824c23..261c70e01e33 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
@@ -279,7 +279,8 @@ void dce110_link_encoder_disable_output(
/* set DP lane settings */
void dce110_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
- const struct link_training_settings *link_settings);
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void dce110_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
index f4b34c110eae..779110a2d948 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
@@ -1101,7 +1101,8 @@ void dcn10_link_encoder_disable_output(
void dcn10_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
- const struct link_training_settings *link_settings)
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
union dpcd_training_lane_set training_lane_set = { { 0 } };
@@ -1116,26 +1117,26 @@ void dcn10_link_encoder_dp_set_lane_settings(
cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl.transmitter = enc10->base.transmitter;
cntl.connector_obj_id = enc10->base.connector;
- cntl.lanes_number = link_settings->link_settings.lane_count;
+ cntl.lanes_number = link_settings->lane_count;
cntl.hpd_sel = enc10->base.hpd_source;
- cntl.pixel_clock = link_settings->link_settings.link_rate *
+ cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
LINK_RATE_REF_FREQ_IN_KHZ;
- for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) {
+ for (lane = 0; lane < link_settings->lane_count; lane++) {
/* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET =
- link_settings->lane_settings[lane].VOLTAGE_SWING;
+ lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET =
- link_settings->lane_settings[lane].PRE_EMPHASIS;
+ lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */
- if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) {
+ if (link_settings->link_rate == LINK_RATE_HIGH2) {
/* this is passed to VBIOS
* to program post cursor 2 level
*/
training_lane_set.bits.POST_CURSOR2_SET =
- link_settings->lane_settings[lane].POST_CURSOR2;
+ lane_settings[lane].POST_CURSOR2;
}
cntl.lane_select = lane;
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index c337588231ff..663aac0a164a 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -581,7 +581,8 @@ void dcn10_link_encoder_disable_output(
/* set DP lane settings */
void dcn10_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
- const struct link_training_settings *link_settings);
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void dcn10_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
index 101444c6f145..2013a70603ae 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
@@ -162,7 +162,8 @@ struct link_encoder_funcs {
void (*disable_output)(struct link_encoder *link_enc,
enum signal_type signal);
void (*dp_set_lane_settings)(struct link_encoder *enc,
- const struct link_training_settings *link_settings);
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void (*dp_set_phy_pattern)(struct link_encoder *enc,
const struct encoder_set_dp_phy_pattern_param *para);
void (*update_mst_stream_allocation_table)(
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index ce9762aa58c9..3400e75685aa 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -97,6 +97,10 @@ struct link_hwss_ext {
void (*set_dp_link_test_pattern)(struct dc_link *link,
const struct link_resource *link_res,
struct encoder_set_dp_phy_pattern_param *tp_params);
+ void (*set_dp_lane_settings)(struct dc_link *link,
+ const struct link_resource *link_res,
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
};
struct link_hwss {
diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
index 348e9a600a72..df8bc44bc4be 100644
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
@@ -63,7 +63,8 @@ static void virtual_link_encoder_disable_output(
static void virtual_link_encoder_dp_set_lane_settings(
struct link_encoder *enc,
- const struct link_training_settings *link_settings) {}
+ const struct dc_link_settings *link_settings,
+ const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {}
static void virtual_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc,
--
2.34.1
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