[PATCH] drm/amd/pm: Prevent divide by zero

[Mr. B34r]

 From: Yefim Barashkin <mr.b34r at kolabnow.com>

divide error: 0000 [#1] SMP PTI
CPU: 3 PID: 78925 Comm: tee Not tainted 5.15.50-1-lts #1
Hardware name: MSI MS-7A59/Z270 SLI PLUS (MS-7A59), BIOS 1.90 01/30/2018
RIP: 0010:smu_v11_0_set_fan_speed_rpm+0x11/0x110 [amdgpu]

Speed is user-configurable through a file.
I accidentally set it to zero, and the driver crashed.

Signed-off-by: Yefim Barashkin <mr.b34r at kolabnow.com>
---
  drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 4 ++++
  1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c 
b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
index 5f8809f6990d..69cebdb58c04 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
@@ -1236,6 +1236,10 @@ int smu_v11_0_set_fan_speed_rpm(struct 
smu_context *smu,
      * - For some Sienna Cichlid SKU, the fan speed cannot be set
      *   lower than 500 RPM.
      */
+
+   if (speed == 0)
+       return -EINVAL;
+
     tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
     WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
              REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
--
2.36.1