[PATCH 3/5] drm/amdgpu: save and restore gc hub regs
Andrey Grodzovsky
andrey.grodzovsky at amd.com
Mon Jul 25 21:18:18 UTC 2022
Acked-by: Andrey Grodzovsky <andrey.grodzovsky at amd.com>
Andrey
On 2022-07-22 03:34, Victor Zhao wrote:
> Save and restore gfxhub regs as they will be reset during mode 2
>
> Signed-off-by: Victor Zhao <Victor.Zhao at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 2 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 26 +++++++
> drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c | 72 +++++++++++++++++++
> drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 7 +-
> .../include/asic_reg/gc/gc_10_3_0_offset.h | 4 ++
> 5 files changed, 110 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> index beabab515836..f8036f2b100e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h
> @@ -35,6 +35,8 @@ struct amdgpu_gfxhub_funcs {
> void (*init)(struct amdgpu_device *adev);
> int (*get_xgmi_info)(struct amdgpu_device *adev);
> void (*utcl2_harvest)(struct amdgpu_device *adev);
> + void (*mode2_save_regs)(struct amdgpu_device *adev);
> + void (*mode2_restore_regs)(struct amdgpu_device *adev);
> };
>
> struct amdgpu_gfxhub {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 008eaca27151..0305b660cd17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -264,6 +264,32 @@ struct amdgpu_gmc {
> u64 mall_size;
> /* number of UMC instances */
> int num_umc;
> + /* mode2 save restore */
> + u64 VM_L2_CNTL;
> + u64 VM_L2_CNTL2;
> + u64 VM_DUMMY_PAGE_FAULT_CNTL;
> + u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32;
> + u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32;
> + u64 VM_L2_PROTECTION_FAULT_CNTL;
> + u64 VM_L2_PROTECTION_FAULT_CNTL2;
> + u64 VM_L2_PROTECTION_FAULT_MM_CNTL3;
> + u64 VM_L2_PROTECTION_FAULT_MM_CNTL4;
> + u64 VM_L2_PROTECTION_FAULT_ADDR_LO32;
> + u64 VM_L2_PROTECTION_FAULT_ADDR_HI32;
> + u64 VM_DEBUG;
> + u64 VM_L2_MM_GROUP_RT_CLASSES;
> + u64 VM_L2_BANK_SELECT_RESERVED_CID;
> + u64 VM_L2_BANK_SELECT_RESERVED_CID2;
> + u64 VM_L2_CACHE_PARITY_CNTL;
> + u64 VM_L2_IH_LOG_CNTL;
> + u64 VM_CONTEXT_CNTL[16];
> + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16];
> + u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16];
> + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16];
> + u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16];
> + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16];
> + u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16];
> + u64 MC_VM_MX_L1_TLB_CNTL;
> };
>
> #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> index d8c531581116..51cf8acd2d79 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c
> @@ -576,6 +576,76 @@ static void gfxhub_v2_1_utcl2_harvest(struct amdgpu_device *adev)
> }
> }
>
> +static void gfxhub_v2_1_save_regs(struct amdgpu_device *adev)
> +{
> + int i;
> + adev->gmc.VM_L2_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
> + adev->gmc.VM_L2_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2);
> + adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL);
> + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32);
> + adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32);
> + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
> + adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2);
> + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3);
> + adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4);
> + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32);
> + adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32 = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32);
> + adev->gmc.VM_DEBUG = RREG32_SOC15(GC, 0, mmGCVM_DEBUG);
> + adev->gmc.VM_L2_MM_GROUP_RT_CLASSES = RREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES);
> + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID);
> + adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2 = RREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2);
> + adev->gmc.VM_L2_CACHE_PARITY_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL);
> + adev->gmc.VM_L2_IH_LOG_CNTL = RREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL);
> +
> + for (i = 0; i <= 15; i++) {
> + adev->gmc.VM_CONTEXT_CNTL[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2);
> + adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i] = RREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2);
> + }
> +
> + adev->gmc.MC_VM_MX_L1_TLB_CNTL = RREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL);
> +}
> +
> +static void gfxhub_v2_1_restore_regs(struct amdgpu_device *adev)
> +{
> + int i;
> + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL, adev->gmc.VM_L2_CNTL);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_CNTL2, adev->gmc.VM_L2_CNTL2);
> + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_CNTL, adev->gmc.VM_DUMMY_PAGE_FAULT_CNTL);
> + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_LO32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_LO32);
> + WREG32_SOC15(GC, 0, mmGCVM_DUMMY_PAGE_FAULT_ADDR_HI32, adev->gmc.VM_DUMMY_PAGE_FAULT_ADDR_HI32);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL2, adev->gmc.VM_L2_PROTECTION_FAULT_CNTL2);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL3, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL3);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_MM_CNTL4, adev->gmc.VM_L2_PROTECTION_FAULT_MM_CNTL4);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_LO32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_LO32);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_ADDR_HI32, adev->gmc.VM_L2_PROTECTION_FAULT_ADDR_HI32);
> + WREG32_SOC15(GC, 0, mmGCVM_DEBUG, adev->gmc.VM_DEBUG);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_MM_GROUP_RT_CLASSES, adev->gmc.VM_L2_MM_GROUP_RT_CLASSES);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_BANK_SELECT_RESERVED_CID2, adev->gmc.VM_L2_BANK_SELECT_RESERVED_CID2);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_CACHE_PARITY_CNTL, adev->gmc.VM_L2_CACHE_PARITY_CNTL);
> + WREG32_SOC15(GC, 0, mmGCVM_L2_IH_LOG_CNTL, adev->gmc.VM_L2_IH_LOG_CNTL);
> +
> + for (i = 0; i <= 15; i++) {
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_CNTL, i, adev->gmc.VM_CONTEXT_CNTL[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[i]);
> + WREG32_SOC15_OFFSET(GC, 0, mmGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32, i * 2, adev->gmc.VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[i]);
> + }
> +
> + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_BASE, adev->gmc.vram_start >> 24);
> + WREG32_SOC15(GC, 0, mmGCMC_VM_FB_LOCATION_TOP, adev->gmc.vram_end >> 24);
> + WREG32_SOC15(GC, 0, mmGCMC_VM_MX_L1_TLB_CNTL, adev->gmc.MC_VM_MX_L1_TLB_CNTL);
> +}
> +
> const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
> .get_fb_location = gfxhub_v2_1_get_fb_location,
> .get_mc_fb_offset = gfxhub_v2_1_get_mc_fb_offset,
> @@ -586,4 +656,6 @@ const struct amdgpu_gfxhub_funcs gfxhub_v2_1_funcs = {
> .init = gfxhub_v2_1_init,
> .get_xgmi_info = gfxhub_v2_1_get_xgmi_info,
> .utcl2_harvest = gfxhub_v2_1_utcl2_harvest,
> + .mode2_save_regs = gfxhub_v2_1_save_regs,
> + .mode2_restore_regs = gfxhub_v2_1_restore_regs,
> };
> diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> index 0512960bed23..51a5b68f77d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c
> @@ -94,8 +94,11 @@ sienna_cichlid_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
> int r = 0;
> struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
>
> - if (!amdgpu_sriov_vf(adev))
> + if (!amdgpu_sriov_vf(adev)) {
> + if (adev->gfxhub.funcs->mode2_save_regs)
> + adev->gfxhub.funcs->mode2_save_regs(adev);
> r = sienna_cichlid_mode2_suspend_ip(adev);
> + }
>
> return r;
> }
> @@ -152,6 +155,8 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev)
> }
>
> /* Reinit GFXHUB */
> + if (adev->gfxhub.funcs->mode2_restore_regs)
> + adev->gfxhub.funcs->mode2_restore_regs(adev);
> adev->gfxhub.funcs->init(adev);
> r = adev->gfxhub.funcs->gart_enable(adev);
> if (r) {
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> index f21554a1c86c..594bffce93a9 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h
> @@ -3129,6 +3129,8 @@
> #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_BASE_IDX 0
> #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 0x15cc
> #define mmGCVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_BASE_IDX 0
> +#define mmGCVM_DEBUG 0x15cd
> +#define mmGCVM_DEBUG_BASE_IDX 0
> #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 0x15ce
> #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_BASE_IDX 0
> #define mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 0x15cf
> @@ -3151,6 +3153,8 @@
> #define mmGCVM_L2_BANK_SELECT_RESERVED_CID2_BASE_IDX 0
> #define mmGCVM_L2_CACHE_PARITY_CNTL 0x15d8
> #define mmGCVM_L2_CACHE_PARITY_CNTL_BASE_IDX 0
> +#define mmGCVM_L2_IH_LOG_CNTL 0x15d9
> +#define mmGCVM_L2_IH_LOG_CNTL_BASE_IDX 0
> #define mmGCVM_L2_CNTL5 0x15dc
> #define mmGCVM_L2_CNTL5_BASE_IDX 0
> #define mmGCVM_L2_GCR_CNTL 0x15dd
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