[PATCH 2/4] Documentation/amdgpu/display: add DC color caps info
Rodrigo Siqueira Jordao
Rodrigo.Siqueira at amd.com
Wed Jul 27 21:21:48 UTC 2022
On 2022-07-17 19:28, Tales Lelo da Aparecida wrote:
> On 16/07/2022 19:25, Melissa Wen wrote:
>> Add details about color correction capabilities and explain a bit about
>> differences between DC hw generations and also how they are mapped
>> between DRM and DC interface. Two schemas for DCN 2.0 and 3.0 (converted
>> to svg from the original png) is included to illustrate it. They were
>> obtained from a discussion[1] in the amd-gfx mailing list.
>>
>> [1]
>> https://lore.kernel.org/amd-gfx/20220422142811.dm6vtk6v64jcwydk@mail.igalia.com/
>>
>>
>> v2:
>>
>> - remove redundant comments (Harry)
>> - fix typo (Harry)
>>
>> Signed-off-by: Melissa Wen <mwen at igalia.com>
>> ---
>> .../amdgpu/display/dcn2_cm_drm_current.svg | 1370 +++++++++++++++
>> .../amdgpu/display/dcn3_cm_drm_current.svg | 1529 +++++++++++++++++
>> .../gpu/amdgpu/display/display-manager.rst | 35 +
>> drivers/gpu/drm/amd/display/dc/dc.h | 74 +-
>> 4 files changed, 2995 insertions(+), 13 deletions(-)
>> create mode 100644
>> Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>> create mode 100644
>> Documentation/gpu/amdgpu/display/dcn3_cm_drm_current.svg
>>
>> diff --git a/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>> b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
>> new file mode 100644
>> index 000000000000..315ffc5a1a4b
>> --- /dev/null
>> +++ b/Documentation/gpu/amdgpu/display/dcn2_cm_drm_current.svg
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>> diff --git a/Documentation/gpu/amdgpu/display/display-manager.rst
>> b/Documentation/gpu/amdgpu/display/display-manager.rst
>> index b1b0f11aed83..8960a5f1fa66 100644
>> --- a/Documentation/gpu/amdgpu/display/display-manager.rst
>> +++ b/Documentation/gpu/amdgpu/display/display-manager.rst
>> @@ -49,3 +49,38 @@ Color Management Properties
>> .. kernel-doc:: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
>> :internal:
>> +
>> +
>> +DC Color Capabilities between DCN generations
>> +---------------------------------------------
>> +
>> +DRM/KMS framework defines three CRTC color correction properties:
>> degamma,
>> +color transformation matrix (ctm) and gamma, and two properties for
>> degamma and
>
> Abbreviations should be written as all-uppercase
> https://docs.kernel.org/gpu/introduction.html?highlight=uppercase#style-guidelines
>
>
>> +gamma lut sizes. AMD DC programs some of the color correction features
>> +pre-blending but DRM/KMS has not per-plane color correction properties.
>> +
>> +What's possible to do before and after blending has changed quite a
>> bit between
>> +DCN generations as it depends on hardware color capabilities. DPP and
>> MPC color
>> +correction caps are described below.
>> +
>> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
>> + :doc: color-management-caps
>> +
>> +.. kernel-doc:: drivers/gpu/drm/amd/display/dc/dc.h
>> + :internal:
>> +
>> +In general, the DRM three properties are programed to DC, as follows:
>> CRT > +gamma after blending, and CRTC degamma pre-blending. Although
>> CTM is
> programmed
>> +after blending, it is mapped to DPP hw blocks (pre-blending). Other
>> color caps
>> +available in the hw is not currently exposed by DRM interface and are by
>> +passed. To illustrate DCN generation capabilities and differences
>> between
>
> possible typo: "by\npassed" -> "bypassed"
>
>> +them, you can compare the color management schemas for DCN 2.0 and
>> DCN 3.0
>> +families below.
>> +
>> +**DCN 2.0 family color caps and mapping**
>> +
>> +.. kernel-figure:: dcn2_cm_drm_current.svg
>> +
>> +**DCN 3.0 family color caps and mapping**
>> +
>> +.. kernel-figure:: dcn3_cm_drm_current.svg
>> diff --git a/drivers/gpu/drm/amd/display/dc/dc.h
>> b/drivers/gpu/drm/amd/display/dc/dc.h
>> index 7c42377f0aae..84275f3974c1 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dc.h
>> +++ b/drivers/gpu/drm/amd/display/dc/dc.h
>> @@ -118,7 +118,26 @@ struct dc_plane_cap {
>> uint32_t min_height;
>> };
>> -// Color management caps (DPP and MPC)
>> +/**
>> + * DOC: color-management-caps
>> + *
>> + * **Color management caps (DPP and MPC)**
>> + *
>> + * Modules/color calculates various colour operations which are
>> translated to
>
> Nit: colour -> color
> The DRM documentation has a **preference** for the american spelling
> https://www.kernel.org/doc/html/latest/gpu/introduction.html?highlight=American%20English#style-guidelines
>
>
>> + * abstracted HW. DCE 5-12 had almost no important changes, but
>> starting with
>> + * DCN1, every new generation comes with fairly major differences in
>> color
>> + * pipeline. Therefore, we abstract color pipe capabilities so
>> modules/DM can
>> + * decide mapping to HW block based on logical capabilities.
>> + */
>> +
>> +/**
>> + * struct rom_curve_caps - predefined transfer function caps for
>> degamma and regamma
>> + * @srgb: RGB color space transfer func
>> + * @bt2020: BT.2020 transfer func
>> + * @gamma2_2: standard gamma
>> + * @pq: perceptual quantizer transfer function
>> + * @hlg: hybrid log–gamma transfer function
>> + */
>> struct rom_curve_caps {
>> uint16_t srgb : 1;
>> uint16_t bt2020 : 1;
>> @@ -127,36 +146,65 @@ struct rom_curve_caps {
>> uint16_t hlg : 1;
>> };
>> +/**
>> + * struct dpp_color_caps - color pipeline capabilities for display
>> pipe and
>> + * plane blocks
>> + *
>> + * @dcn_arch: all DCE generations treated the same
>> + * @input_lut_shared: shared with DGAM. Input lut is different than
>> most LUTs,
>> + * just plain 256-entry lookup
>> + * @icsc: input color space conversion
>
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter
> or member 'dgam_ram' not described in 'dpp_color_caps'
Hi,
I was trying to figure out the meaning of some of these fields.
First of all, and in the LUT context, notice that some fields have the
prefix _ram, and others have _rom. When you see the ram, it means that
we have a hardware LUT in the device, and we can program its values. If
you see rom, it also means that we have hardware LUT but have
pre-hardcoded values, which means that we can only select between a few
of them (e.g., sRGB, PQ, etc.). I guess ROM is preferable since it
requires less configuration.
>
>> + * @post_csc: post color space conversion, before gamut remap
>> + * @gamma_corr: degamma correction
>> + * @hw_3d_lut: 3d lut support. It implies a shaper LUT before, it may
>> be shared
>> + * with MPC by setting mpc:shared_3d_lut flag
>> + * @ogam_ram: blend gamma
dgam refers to 'degamma'
and
ogam to 'out gamma'.
>> + * @ocsc: output color space conversion
>
> ./drivers/gpu/drm/amd/display/dc/dc.h:181: warning: Function parameter
> or member 'dgam_rom_for_yuv' not described in 'dpp_color_caps'
dgam_rom_for_yuv -> I don't know precisely why we have this, but since
DCN3 introduced it, I guess this is a specific behavior to compute yuv.
afaik, this caps stands for capabilities, i.e., dpp_color_caps describes
the DPP color capabilities configured for the specific hardware and setup.
Best Regards
Siqueira
>
>> + * @dgam_rom_caps: caps for degamma
>> + * @ogam_rom_caps: caps for regamma 1D lut
>> + *
>> + * Note: hdr_mult and gamut remap (ctm) are always available in DPP
>> (in that order)
>> + */
>> struct dpp_color_caps {
>> - uint16_t dcn_arch : 1; // all DCE generations treated the same
>> - // input lut is different than most LUTs, just plain 256-entry
>> lookup
>> - uint16_t input_lut_shared : 1; // shared with DGAM
>> + uint16_t dcn_arch : 1;
>> + uint16_t input_lut_shared : 1;
>> uint16_t icsc : 1;
>> uint16_t dgam_ram : 1;
>> - uint16_t post_csc : 1; // before gamut remap
>> + uint16_t post_csc : 1;
>> uint16_t gamma_corr : 1;
>> -
>> - // hdr_mult and gamut remap always available in DPP (in that order)
>> - // 3d lut implies shaper LUT,
>> - // it may be shared with MPC - check MPC:shared_3d_lut flag
>> uint16_t hw_3d_lut : 1;
>> - uint16_t ogam_ram : 1; // blnd gam
>> + uint16_t ogam_ram : 1;
>> uint16_t ocsc : 1;
>> uint16_t dgam_rom_for_yuv : 1;
>> struct rom_curve_caps dgam_rom_caps;
>> struct rom_curve_caps ogam_rom_caps;
>> };
>> +/**
>> + * struct mpc_color_caps - color pipeline capabilities for multiple
>> pipe and
>> + * plane combined blocks
>> + *
>> + * @gamut_remap: color transformation matrix
>
> ./drivers/gpu/drm/amd/display/dc/dc.h:201: warning: Function parameter
> or member 'ogam_ram' not described in 'mpc_color_caps'
>
>> + * @ocsc: output color space conversion matrix
>> + * @num_3dluts: 3d lut, always assumes a preceding shaper LUT
>> + * @shared_3d_lut: shared 3d lut flag, can be either DPP or MPC, but
>> single
>> + * instance
>> + * @ogam_rom_caps: caps for regama 1d lut
>
> typo: regama -> regamma
>
>> + */
>> struct mpc_color_caps {
>> uint16_t gamut_remap : 1;
>> uint16_t ogam_ram : 1;
>> uint16_t ocsc : 1;
>> - uint16_t num_3dluts : 3; //3d lut always assumes a preceding
>> shaper LUT
>> - uint16_t shared_3d_lut:1; //can be in either DPP or MPC, but
>> single instance
>> -
>> + uint16_t num_3dluts : 3;
>> + uint16_t shared_3d_lut:1;
>> struct rom_curve_caps ogam_rom_caps;
>> };
>> +/**
>> + * struct dc_color_caps - color pipes capabilities for DPP and MPC hw
>> blocks
>> + * @dpp: color pipes caps for DPP
>> + * @mpc: color pipes caps for MPC
>> + */
>> struct dc_color_caps {
>> struct dpp_color_caps dpp;
>> struct mpc_color_caps mpc;
>
>
> Again, thanks for the documentation patch!
>
> Kind regards,
> Tales Aparecida
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