[PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code

[Alex Deucher]

On Thu, Jul 28, 2022 at 4:34 PM Rodrigo Siqueira
<Rodrigo.Siqueira at amd.com> wrote:
>
> We got a report from Stephen/Michael that the PowerPC build was failing
> with the following error:
>
> ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
> ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
>
> This error happened because of the function optc3_set_vrr_m_const. This
> function expects a double as a parameter in a code that is not allowed
> to have FPU operations. After further investigation, it became clear
> that optc3_set_vrr_m_const was never invoked, so we can safely drop this
> function and fix the ld issue.
>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Cc: Melissa Wen <mwen at igalia.com>
> Reported-by: Stephen Rothwell <sfr at canb.auug.org.au>
> Reported-by: Michael Ellerman <mpe at ellerman.id.au>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c        | 8 --------
>  drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h        | 3 ---
>  drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c        | 1 -
>  drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
>  4 files changed, 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> index d072997477dd..1782b9c26cf4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
> @@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
>         REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
>  }
>
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> -               double vtotal_avg)
> -{
> -       DC_FP_START();
> -       optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
> -       DC_FP_END();
> -}
> -
>  void optc3_set_odm_bypass(struct timing_generator *optc,
>                 const struct dc_crtc_timing *dc_crtc_timing)
>  {
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> index 33bd12f5dc17..dd45a5499b07 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
> @@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
>
>  void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
>
> -void optc3_set_vrr_m_const(struct timing_generator *optc,
> -               double vtotal_avg);
> -
>  void optc3_set_drr_trigger_window(struct timing_generator *optc,
>                 uint32_t window_start, uint32_t window_end);
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> index 992e56c6907e..eff1f4e17689 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
> @@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
>                 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
>                 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
>                 .enable_optc_clock = optc1_enable_optc_clock,
> -               .set_vrr_m_const = optc3_set_vrr_m_const,
>                 .set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted
>                 .get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
>                 .set_vtotal_min_max = optc3_set_vtotal_min_max,
> diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> index 62d4683f17a2..4cfa733cf96f 100644
> --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
> @@ -302,8 +302,6 @@ struct timing_generator_funcs {
>                         int group_idx,
>                         uint32_t gsl_ready_signal);
>         void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
> -       void (*set_vrr_m_const)(struct timing_generator *optc,
> -                       double vtotal_avg);
>         void (*set_drr_trigger_window)(struct timing_generator *optc,
>                         uint32_t window_start, uint32_t window_end);
>         void (*set_vtotal_change_limit)(struct timing_generator *optc,
> --
> 2.35.1
>