[PATCH] drm/amd/display: Add a missing register field for HPO DP stream encoder

[Alex Deucher]

Acked-by: Alex Deucher <alexander.deucher at amd.com>

On Fri, Jul 29, 2022 at 1:42 PM Aurabindo Pillai
<aurabindo.pillai at amd.com> wrote:
>
> [Why&How]
> Add the missing definition to set the register field
> HBLANK_MINIMUM_SYMBOL_WIDTH
>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai at amd.com>
> ---
>  .../gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> index 7c77c71591a0..82c3b3ac1f0d 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h
> @@ -162,7 +162,8 @@
>         SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, mask_sh),\
>         SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, mask_sh),\
>         SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\
> -       SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh)
> +       SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh),\
> +       SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_HBLANK_CONTROL, HBLANK_MINIMUM_SYMBOL_WIDTH, mask_sh)
>
>
>  #define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \
> --
> 2.37.1
>