[PATCH 5/6] drm/amd/display: Reduce frame size in the bouding box for DCN21

[Harry Wentland]

On 2022-06-03 14:50, Rodrigo Siqueira wrote:
> GCC throw warnings for the function dcn21_update_bw_bounding_box and
> dcn316_update_bw_bounding_box due to its frame size that looks like
> this:
> 
>  error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
> 
> For fixing this issue I dropped an intermadiate variable.
> 
> Cc: Stephen Rothwell <sfr at canb.auug.org.au>
> Cc: Hamza Mahfooz <hamza.mahfooz at amd.com>
> Cc: Aurabindo Pillai <aurabindo.pillai at amd.com>
> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>

Reviewed-by: Harry Wentland <harry.wentland at amd.com>

Harry

> ---
>  .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 29 +++++++++----------
>  1 file changed, 13 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> index d9cc178f6980..c2fec0d85da4 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
> @@ -2004,7 +2004,6 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>  {
>  	struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
>  	struct clk_limit_table *clk_table = &bw_params->clk_table;
> -	struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
>  	unsigned int i, closest_clk_lvl = 0, k = 0;
>  	int j;
>  
> @@ -2017,7 +2016,7 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>  	ASSERT(clk_table->num_entries);
>  	/* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
>  	for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
> -		clock_limits[i] = dcn2_1_soc.clock_limits[i];
> +		dcn2_1_soc.clock_limits[i] = dcn2_1_soc.clock_limits[i];
>  	}
>  
>  	for (i = 0; i < clk_table->num_entries; i++) {
> @@ -2033,24 +2032,22 @@ void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params
>  		if (i == 1)
>  			k++;
>  
> -		clock_limits[k].state = k;
> -		clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> -		clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> -		clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
> -		clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
> +		dcn2_1_soc.clock_limits[k].state = k;
> +		dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
> +		dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
> +		dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
> +		dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
>  
> -		clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> -		clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> -		clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> -		clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> -		clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> -		clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> -		clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
> +		dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
> +		dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
> +		dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
> +		dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
> +		dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
> +		dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
> +		dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
>  
>  		k++;
>  	}
> -	for (i = 0; i < clk_table->num_entries + 1; i++)
> -		dcn2_1_soc.clock_limits[i] = clock_limits[i];
>  	if (clk_table->num_entries) {
>  		dcn2_1_soc.num_states = clk_table->num_entries + 1;
>  		/* fill in min DF PState */