[PATCH] drm/amdgpu: always flush the TLB on gfx8

[Alex Deucher]

yes. will do.

Alex

On Wed, Jun 8, 2022 at 9:58 AM Christian König
<ckoenig.leichtzumerken at gmail.com> wrote:
>
> Am 07.06.22 um 22:27 schrieb Alex Deucher:
> > On Fri, Jun 3, 2022 at 9:05 AM Christian König
> > <ckoenig.leichtzumerken at gmail.com> wrote:
> >> The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits
> >> are set.
> >>
> >> Signed-off-by: Christian König <christian.koenig at amd.com>
> > Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
> Alex could you push this? It's an important fix, but I'm seriously not
> feeling well at the moment.
>
> Thanks,
> Christian.
>
> >
> >> ---
> >>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
> >>   1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> index 9596c22fded6..b747488c28ad 100644
> >> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >> @@ -847,6 +847,11 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> >>          flush_tlb |= adev->gmc.xgmi.num_physical_nodes &&
> >>                       adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0);
> >>
> >> +       /*
> >> +        * On GFX8 and older any 8 PTE block with a valid bit set enters the TLB
> >> +        */
> >> +       flush_tlb |= adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 0, 0);
> >> +
> >>          memset(&params, 0, sizeof(params));
> >>          params.adev = adev;
> >>          params.vm = vm;
> >> --
> >> 2.25.1
> >>
>