[PATCH 13/23] drm/amd/display: Fix comments
Hamza Mahfooz
hamza.mahfooz at amd.com
Fri Jun 10 20:52:35 UTC 2022
From: Samson Tam <Samson.Tam at amd.com>
[Why & how]
Fix format and typo of comments.
Acked-by: Alan Liu <HaoPing.Liu at amd.com>
Signed-off-by: Samson Tam <Samson.Tam at amd.com>
---
.../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 1 -
drivers/gpu/drm/amd/display/dc/core/dc_link.c | 8 ++++++--
.../dc/gpio/dcn20/hw_translate_dcn20.c | 17 ++++++++++-------
.../dc/gpio/dcn21/hw_translate_dcn21.c | 17 ++++++++++-------
.../dc/gpio/dcn30/hw_translate_dcn30.c | 19 +++++++++++--------
5 files changed, 37 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index cac80ba69072..fb82e9f9738e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -436,7 +436,6 @@ void dcn2_read_clocks_from_hw_dentist(struct clk_mgr *clk_mgr_base)
clk_mgr_base->clks.dppclk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
* clk_mgr->base.dentist_vco_freq_khz) / dpp_divider;
}
-
}
void dcn2_get_clock(struct clk_mgr *clk_mgr,
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 7884530cc02b..199868925fe4 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1379,7 +1379,9 @@ bool dc_link_get_hpd_state(struct dc_link *dc_link)
static enum hpd_source_id get_hpd_line(struct dc_link *link)
{
struct gpio *hpd;
- enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
+ enum hpd_source_id hpd_id;
+
+ hpd_id = HPD_SOURCEID_UNKNOWN;
hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
link->ctx->gpio_service);
@@ -1418,7 +1420,9 @@ static enum hpd_source_id get_hpd_line(struct dc_link *link)
static enum channel_id get_ddc_line(struct dc_link *link)
{
struct ddc *ddc;
- enum channel_id channel = CHANNEL_ID_UNKNOWN;
+ enum channel_id channel;
+
+ channel = CHANNEL_ID_UNKNOWN;
ddc = dal_ddc_service_get_ddc_pin(link->ddc);
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
index 52ba62b3b5e4..3005ee7751a0 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c
@@ -150,7 +150,8 @@ static bool offset_to_id(
/* DDC */
/* we don't care about the GPIO_ID for DDC
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
- * directly in the create method */
+ * directly in the create method
+ */
case REG(DC_GPIO_DDC1_A):
*en = GPIO_DDC_LINE_DDC1;
return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
*en = GPIO_DDC_LINE_DDC_VGA;
return true;
-// case REG(DC_GPIO_I2CPAD_A): not exit
-// case REG(DC_GPIO_PWRSEQ_A):
-// case REG(DC_GPIO_PAD_STRENGTH_1):
-// case REG(DC_GPIO_PAD_STRENGTH_2):
-// case REG(DC_GPIO_DEBUG):
+/*
+ * case REG(DC_GPIO_I2CPAD_A): not exit
+ * case REG(DC_GPIO_PWRSEQ_A):
+ * case REG(DC_GPIO_PAD_STRENGTH_1):
+ * case REG(DC_GPIO_PAD_STRENGTH_2):
+ * case REG(DC_GPIO_DEBUG):
+ */
/* UNEXPECTED */
default:
-// case REG(DC_GPIO_SYNCA_A): not exist
+/* case REG(DC_GPIO_SYNCA_A): not exist */
ASSERT_CRITICAL(false);
return false;
}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
index 291966efe63d..d734e3a134d1 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c
@@ -153,7 +153,8 @@ static bool offset_to_id(
/* DDC */
/* we don't care about the GPIO_ID for DDC
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
- * directly in the create method */
+ * directly in the create method
+ */
case REG(DC_GPIO_DDC1_A):
*en = GPIO_DDC_LINE_DDC1;
return true;
@@ -173,14 +174,16 @@ static bool offset_to_id(
*en = GPIO_DDC_LINE_DDC_VGA;
return true;
-// case REG(DC_GPIO_I2CPAD_A): not exit
-// case REG(DC_GPIO_PWRSEQ_A):
-// case REG(DC_GPIO_PAD_STRENGTH_1):
-// case REG(DC_GPIO_PAD_STRENGTH_2):
-// case REG(DC_GPIO_DEBUG):
+/*
+ * case REG(DC_GPIO_I2CPAD_A): not exit
+ * case REG(DC_GPIO_PWRSEQ_A):
+ * case REG(DC_GPIO_PAD_STRENGTH_1):
+ * case REG(DC_GPIO_PAD_STRENGTH_2):
+ * case REG(DC_GPIO_DEBUG):
+ */
/* UNEXPECTED */
default:
-// case REG(DC_GPIO_SYNCA_A): not exist
+/* case REG(DC_GPIO_SYNCA_A): not exista */
#ifdef PALLADIUM_SUPPORTED
*id = GPIO_ID_HPD;
*en = GPIO_DDC_LINE_DDC1;
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
index 3169c567475f..49d6250037a9 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/dcn30/hw_translate_dcn30.c
@@ -155,7 +155,8 @@ static bool offset_to_id(
/* DDC */
/* we don't care about the GPIO_ID for DDC
* in DdcHandle it will use GPIO_ID_DDC_DATA/GPIO_ID_DDC_CLOCK
- * directly in the create method */
+ * directly in the create method
+ */
case REG(DC_GPIO_DDC1_A):
*en = GPIO_DDC_LINE_DDC1;
return true;
@@ -178,14 +179,16 @@ static bool offset_to_id(
*en = GPIO_DDC_LINE_DDC_VGA;
return true;
-// case REG(DC_GPIO_I2CPAD_A): not exit
-// case REG(DC_GPIO_PWRSEQ_A):
-// case REG(DC_GPIO_PAD_STRENGTH_1):
-// case REG(DC_GPIO_PAD_STRENGTH_2):
-// case REG(DC_GPIO_DEBUG):
+/*
+ * case REG(DC_GPIO_I2CPAD_A): not exit
+ * case REG(DC_GPIO_PWRSEQ_A):
+ * case REG(DC_GPIO_PAD_STRENGTH_1):
+ * case REG(DC_GPIO_PAD_STRENGTH_2):
+ * case REG(DC_GPIO_DEBUG):
+ */
/* UNEXPECTED */
default:
-// case REG(DC_GPIO_SYNCA_A): not exist
+/* case REG(DC_GPIO_SYNCA_A): not exist */
ASSERT_CRITICAL(false);
return false;
}
@@ -369,7 +372,7 @@ static const struct hw_translate_funcs funcs = {
};
/*
- * dal_hw_translate_dcn10_init
+ * dal_hw_translate_dcn30_init
*
* @brief
* Initialize Hw translate function pointers.
--
2.36.1
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