[PATCH] drm/amdgpu/vcn: adjust unified queue code format

Christian König ckoenig.leichtzumerken at gmail.com
Wed Jun 15 07:51:03 UTC 2022


Am 15.06.22 um 04:56 schrieb Ruijing Dong:
> Fixed some errors and warnings found by checkpatch.pl.
>
> Signed-off-by: Ruijing Dong <ruijing.dong at amd.com>

Acked-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 12 ++++++------
>   drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c   |  8 ++++----
>   2 files changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index e62ff7db4736..fea436023351 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -730,8 +730,8 @@ int amdgpu_vcn_dec_ring_test_ib(struct amdgpu_ring *ring, long timeout)
>   	return r;
>   }
>   
> -static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
> -					  uint32_t ib_pack_in_dw, bool enc)
> +static uint32_t *amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
> +						uint32_t ib_pack_in_dw, bool enc)
>   {
>   	uint32_t *ib_checksum;
>   
> @@ -749,7 +749,7 @@ static uint32_t * amdgpu_vcn_unified_ring_ib_header(struct amdgpu_ib *ib,
>   }
>   
>   static void amdgpu_vcn_unified_ring_ib_checksum(uint32_t **ib_checksum,
> -				        uint32_t ib_pack_in_dw)
> +						uint32_t ib_pack_in_dw)
>   {
>   	uint32_t i;
>   	uint32_t checksum = 0;
> @@ -790,7 +790,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
>   	/* single queue headers */
>   	if (sq) {
>   		ib_pack_in_dw = sizeof(struct amdgpu_vcn_decode_buffer) / sizeof(uint32_t)
> -			                     + 4 + 2; /* engine info + decoding ib in dw */
> +						+ 4 + 2; /* engine info + decoding ib in dw */
>   		ib_checksum = amdgpu_vcn_unified_ring_ib_header(ib, ib_pack_in_dw, false);
>   	}
>   
> @@ -896,7 +896,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>   					 struct amdgpu_ib *ib_msg,
>   					 struct dma_fence **fence)
>   {
> -	unsigned ib_size_dw = 16;
> +	unsigned int ib_size_dw = 16;
>   	struct amdgpu_job *job;
>   	struct amdgpu_ib *ib;
>   	struct dma_fence *f = NULL;
> @@ -962,7 +962,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>   					  struct amdgpu_ib *ib_msg,
>   					  struct dma_fence **fence)
>   {
> -	unsigned ib_size_dw = 16;
> +	unsigned int ib_size_dw = 16;
>   	struct amdgpu_job *job;
>   	struct amdgpu_ib *ib;
>   	struct dma_fence *f = NULL;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> index d6f134ef9633..84ac2401895a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
> @@ -120,7 +120,7 @@ static int vcn_v4_0_sw_init(void *handle)
>   		sprintf(ring->name, "vcn_unified_%d", i);
>   
>   		r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[i].irq, 0,
> -				  AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
> +						AMDGPU_RING_PRIO_0, &adev->vcn.inst[i].sched_score);
>   		if (r)
>   			return r;
>   
> @@ -907,7 +907,7 @@ static int vcn_v4_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
>   	WREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR, 0);
>   	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, 0);
>   
> -	tmp= RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
> +	tmp = RREG32_SOC15(VCN, inst_idx, regUVD_RB_RPTR);
>   	WREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR, tmp);
>   	ring->wptr = RREG32_SOC15(VCN, inst_idx, regUVD_RB_WPTR);
>   
> @@ -1048,8 +1048,8 @@ static int vcn_v4_0_start(struct amdgpu_device *adev)
>   
>   				dev_err(adev->dev, "VCN[%d] is not responding, trying to reset the VCPU!!!\n", i);
>   				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL),
> -						UVD_VCPU_CNTL__BLK_RST_MASK,
> -						~UVD_VCPU_CNTL__BLK_RST_MASK);
> +							UVD_VCPU_CNTL__BLK_RST_MASK,
> +							~UVD_VCPU_CNTL__BLK_RST_MASK);
>   				mdelay(10);
>   				WREG32_P(SOC15_REG_OFFSET(VCN, i, regUVD_VCPU_CNTL), 0,
>   						~UVD_VCPU_CNTL__BLK_RST_MASK);



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