[PATCH 6/7] drm/amdgpu/mes: add mes ring test

[Lang Yu]

On 06/29/ , Jack Xiao wrote:
> Use read/write register to test mes ring.
> 
> Signed-off-by: Jack Xiao <Jack.Xiao at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 36 +++++++++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/mes_v11_0.c  |  6 +++++
>  3 files changed, 43 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> index b6c2a5058b64..c18ea0bc00eb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
> @@ -926,6 +926,42 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
>  	return r;
>  }
>  
> +int amdgpu_mes_ring_test_ring(struct amdgpu_device *adev)
> +{
> +	uint32_t scratch;
> +	uint32_t tmp = 0;
> +	unsigned i;
> +	int r = 0;
> +
> +	r = amdgpu_gfx_scratch_get(adev, &scratch);

amdgpu_gfx_scratch_get/free() have been removed in latest amd-staging-drm-next.
See e9b8129d8ca5 (drm/amdgpu: nuke dynamic gfx scratch reg allocation).

Regards,
Lang

> +	if (r) {
> +		DRM_ERROR("amdgpu: mes failed to get scratch reg (%d).\n", r);
> +		return r;
> +	}
> +
> +	WREG32(scratch, 0xCAFEDEAD);
> +
> +	tmp = amdgpu_mes_rreg(adev, scratch);
> +	if (tmp != 0xCAFEDEAD) {
> +		DRM_ERROR("mes failed to read register\n");
> +		goto error;
> +	}
> +
> +	r = amdgpu_mes_wreg(adev, scratch, 0xDEADBEEF);
> +	if (r)
> +		goto error;
> +
> +	tmp = RREG32(scratch);
> +	if (tmp != 0xDEADBEEF) {
> +		DRM_ERROR("mes failed to write register\n");
> +		r = -EIO;
> +	}
> +
> +error:
> +	amdgpu_gfx_scratch_free(adev, scratch);
> +	return r;
> +}
> +
>  static void
>  amdgpu_mes_ring_to_queue_props(struct amdgpu_device *adev,
>  			       struct amdgpu_ring *ring,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> index 93b2ba817916..81610e3f3059 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
> @@ -341,6 +341,7 @@ int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
>  int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
>  				  uint32_t reg0, uint32_t reg1,
>  				  uint32_t ref, uint32_t mask);
> +int amdgpu_mes_ring_test_ring(struct amdgpu_device *adev);
>  
>  int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
>  			int queue_type, int idx,
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 2a6c7a680c62..c4d085429d26 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1194,6 +1194,12 @@ static int mes_v11_0_hw_init(void *handle)
>  		goto failure;
>  	}
>  
> +	r = amdgpu_mes_ring_test_ring(adev);
> +	if (r) {
> +		DRM_ERROR("MES ring test failed\n");
> +		goto failure;
> +	}
> +
>  	/*
>  	 * Disable KIQ ring usage from the driver once MES is enabled.
>  	 * MES uses KIQ ring exclusively so driver cannot access KIQ ring
> -- 
> 2.35.1
>