[PATCH 18/21] drm/amd/display: Fix compile error from TO_CLK_MGR_INTERNAL

[Alan Liu]

From: Leo Li <sunpeng.li at amd.com>

[Why]

On LNX, TO_CLK_MGR_INTERNAL() only works to get clk_mgr_internal from a
given clk_mgr. In clk_mgr_dcn316 struct, the clk_mgr_internal is already
a memeber by the alias 'base'

[How]

Use &clk_mgr->base instead.

Reviewed-by: Harry Wentland <Harry.Wentland at amd.com>
Acked-by: Alan Liu <HaoPing.Liu at amd.com>
Signed-off-by: Leo Li <sunpeng.li at amd.com>
---
 .../dc/clk_mgr/dcn316/dcn316_clk_mgr.c        |  5 +++-
 .../display/dc/clk_mgr/dcn316/dcn316_smu.c    | 26 +++++++++++++++++++
 .../display/dc/clk_mgr/dcn316/dcn316_smu.h    |  2 ++
 3 files changed, 32 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index 43120a8f8305..702d00ce7da4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -683,8 +683,11 @@ void dcn316_clk_mgr_construct(
 	}
 
 	clk_mgr->base.base.dprefclk_khz = 600000;
-	clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
+	clk_mgr->base.base.dprefclk_khz = dcn316_smu_get_dpref_clk(&clk_mgr->base);
+ 	clk_mgr->base.dccg->ref_dtbclk_khz = clk_mgr->base.base.dprefclk_khz;
 	dce_clock_read_ss_info(&clk_mgr->base);
+	clk_mgr->base.dccg->ref_dtbclk_khz =
+	dce_adjust_dp_ref_freq_for_ss(&clk_mgr->base, clk_mgr->base.base.dprefclk_khz);
 
 	clk_mgr->base.base.bw_params = &dcn316_bw_params;
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
index 128614dff108..dceec4b96052 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.c
@@ -310,3 +310,29 @@ void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
 			VBIOSSMC_MSG_SetDtbclkFreq,
 			enable);
 }
+
+int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr)
+{
+	int dprefclk_get_mhz = -1;
+
+	if (clk_mgr->smu_present) {
+		dprefclk_get_mhz = dcn316_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_GetDprefclkFreq,
+			0);
+	}
+	return (dprefclk_get_mhz * 1000);
+}
+
+int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr)
+{
+	int fclk_get_mhz = -1;
+
+	if (clk_mgr->smu_present) {
+		fclk_get_mhz = dcn316_smu_send_msg_with_param(
+			clk_mgr,
+			VBIOSSMC_MSG_GetFclkFrequency,
+			0);
+	}
+	return (fclk_get_mhz * 1000);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
index 658b36d0e107..2a7293f66515 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_smu.h
@@ -133,5 +133,7 @@ void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
 void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
 void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
 void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
+int dcn316_smu_get_dpref_clk(struct clk_mgr_internal *clk_mgr);
+int dcn316_smu_get_smu_fclk(struct clk_mgr_internal *clk_mgr);
 
 #endif /* DAL_DC_316_SMU_H_ */
-- 
2.25.1