[PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1

[James Zhu]

ThispatchisReviewed-by:JamesZhu<James.Zhu at amd.com>

On 2022-03-21 4:26 a.m., Emily Deng wrote:
> Correct the code error for setting register UVD_GFX10_ADDR_CONFIG.
> Need to use inst_idx, or it only will set VCN0.
>
> Signed-off-by: Emily Deng<Emily.Deng at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c87263ed20ec..b16c56aa2d22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -575,8 +575,8 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
>   			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
>   
>   	/* VCN global tiling registers */
> -	WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
> -		UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> +	WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> +		UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
>   }
>   
>   static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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