[PATCH] drm/amdgpu: Add unique_id support for sienna cichlid

[Alex Deucher]

On Fri, Mar 25, 2022 at 9:05 AM Kent Russell <kent.russell at amd.com> wrote:
>
> This is being added to SMU Metrics, so add the required tie-ins in the
> kernel. Also create the corresponding unique_id sysfs file.
>
> v2: Add FW version check, remove SMU mutex
>
> Signed-off-by: Kent Russell <kent.russell at amd.com>
> ---
>  drivers/gpu/drm/amd/pm/amdgpu_pm.c            |  3 +-
>  .../pmfw_if/smu11_driver_if_sienna_cichlid.h  | 12 +++++--
>  .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 35 +++++++++++++++++++
>  3 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> index 5cd67ddf8495..1ed13bf77cbc 100644
> --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
> @@ -1990,7 +1990,8 @@ static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_
>                 if (asic_type != CHIP_VEGA10 &&
>                     asic_type != CHIP_VEGA20 &&
>                     asic_type != CHIP_ARCTURUS &&
> -                   asic_type != CHIP_ALDEBARAN)
> +                   asic_type != CHIP_ALDEBARAN &&
> +                   asic_type != CHIP_SIENNA_CICHLID)

As a follow on or precursor patch, we should convert this to IP
version checks.  Also, you may want to switch the logic here and mark
the attr as supported only if it matches one of the chips that
supports it.

Alex


>                         *states = ATTR_STATE_UNSUPPORTED;
>         } else if (DEVICE_ATTR_IS(pp_features)) {
>                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> index 3e4a314ef925..58f977320d06 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h
> @@ -1419,8 +1419,12 @@ typedef struct {
>    uint8_t  PcieRate               ;
>    uint8_t  PcieWidth              ;
>    uint16_t AverageGfxclkFrequencyTarget;
> -  uint16_t Padding16_2;
>
> +  //PMFW-8711
> +  uint32_t PublicSerialNumLower32;
> +  uint32_t PublicSerialNumUpper32;
> +
> +  uint16_t Padding16_2;
>  } SmuMetrics_t;
>
>  typedef struct {
> @@ -1476,8 +1480,12 @@ typedef struct {
>    uint8_t  PcieRate               ;
>    uint8_t  PcieWidth              ;
>    uint16_t AverageGfxclkFrequencyTarget;
> -  uint16_t Padding16_2;
>
> +  //PMFW-8711
> +  uint32_t PublicSerialNumLower32;
> +  uint32_t PublicSerialNumUpper32;
> +
> +  uint16_t Padding16_2;
>  } SmuMetrics_V2_t;
>
>  typedef struct {
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index 38f04836c82f..39d12bc6daaa 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -481,6 +481,40 @@ static int sienna_cichlid_setup_pptable(struct smu_context *smu)
>         return sienna_cichlid_patch_pptable_quirk(smu);
>  }
>
> +static void sienna_cichlid_get_unique_id(struct smu_context *smu)
> +{
> +       struct amdgpu_device *adev = smu->adev;
> +       struct smu_table_context *smu_table = &smu->smu_table;
> +       SmuMetrics_t *metrics =
> +               &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
> +       SmuMetrics_V2_t *metrics_v2 =
> +               &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
> +       uint32_t upper32 = 0, lower32 = 0;
> +       int ret;
> +
> +       /* Only supported as of version 0.58.83.0 */
> +       if (smu->smc_fw_version < 0x3A5300)
> +               return;
> +
> +       ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
> +       if (ret)
> +               goto out_unlock;
> +
> +       bool use_metrics_v2 = ((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)) &&
> +               (smu->smc_fw_version >= 0x3A4300)) ? true : false;
> +
> +       upper32 = use_metrics_v2 ? metrics_v2->PublicSerialNumUpper32 :
> +                                  metrics->PublicSerialNumUpper32;
> +       lower32 = use_metrics_v2 ? metrics_v2->PublicSerialNumLower32 :
> +                                  metrics->PublicSerialNumLower32;
> +
> +out_unlock:
> +
> +       adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
> +       if (adev->serial[0] == '\0')
> +               sprintf(adev->serial, "%016llx", adev->unique_id);
> +}
> +
>  static int sienna_cichlid_tables_init(struct smu_context *smu)
>  {
>         struct smu_table_context *smu_table = &smu->smu_table;
> @@ -4182,6 +4216,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
>         .get_ecc_info = sienna_cichlid_get_ecc_info,
>         .get_default_config_table_settings = sienna_cichlid_get_default_config_table_settings,
>         .set_config_table = sienna_cichlid_set_config_table,
> +       .get_unique_id = sienna_cichlid_get_unique_id,
>  };
>
>  void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
> --
> 2.25.1
>