[PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address

[Liang, Prike]

[Public]

Thanks for the correcting fix and  I confirm on the gfx1037 exactly need update the mmGCR_GENERAL_CNTL offset to 0x1580.

Meanwhile, please confirm whether this change also apply in the gfx1036, anyway this patch is

Acked-by: Prike Liang <Prike.Liang at amd.com>

> -----Original Message-----
> From: Ji, Ruili <Ruili.Ji at amd.com>
> Sent: Monday, March 28, 2022 11:47 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Huang, Ray
> <Ray.Huang at amd.com>; Liu, Aaron <Aaron.Liu at amd.com>; Zhang, Yifan
> <Yifan1.Zhang at amd.com>; Liang, Prike <Prike.Liang at amd.com>; Ji, Ruili
> <Ruili.Ji at amd.com>
> Subject: [PATCH] drm/amdgpu: fix incorrect GCR_GENERAL_CNTL address
>
> From: Ruili Ji <ruiliji2 at amd.com>
>
> RMB shall use 0x1580 address for GCR_GENERAL_CNTL
>
> Signed-off-by: Ruili Ji <ruiliji2 at amd.com>
> Change-Id: I10a85891986f31411f85fa3db46970aaa8a5bd03
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 99df18ae7316..e4c9d92ac381 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3300,7 +3300,7 @@ static const struct soc15_reg_golden
> golden_settings_gc_10_3_3[] =
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff,
> 0x00000280),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff,
> 0x00800000),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x00000242),
> -     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1ffff, 0x00000500),
> +     SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff,
> +0x00000500),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff,
> 0x000000e4),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x77777777, 0x32103210),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x77777777, 0x32103210), @@ -3436,7 +3436,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_6[] =
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff,
> 0x00000280),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff,
> 0x00800000),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x00000042),
> -     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1ffff, 0x00000500),
> +     SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff,
> +0x00000500),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff,
> 0x00000044),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x77777777, 0x32103210),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x77777777, 0x32103210), @@ -3461,7 +3461,7 @@ static const struct
> soc15_reg_golden golden_settings_gc_10_3_7[] = {
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff,
> 0x00000280),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff,
> 0x00800000),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG,
> 0x0c1807ff, 0x00000041),
> -     SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL,
> 0x1ff1ffff, 0x00000500),
> +     SOC15_REG_GOLDEN_VALUE(GC, 0,
> mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff,
> +0x00000500),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff,
> 0x000000e4),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0,
> 0x77777777, 0x32103210),
>       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1,
> 0x77777777, 0x32103210),
> --
> 2.25.1