[cedar] DMA ring test timeout

Amol suratiamol at gmail.com
Fri May 6 02:41:05 UTC 2022


Hello,

While trying to program the HD 7350 Cedar GPU to run with DPM
under the 157MHz/200MHz sclk/mclk powerstate, for single_display,
and with forced LOW performance on the SMC, the DMA ring seems
to hang.

After the desired power state is programmed, the DMA and CP rings
0xcafedead tests are run. The CP ring test succeeds but the DMA ring
test times out. Note that the Linux radeon driver does not wait so late
during its initialization to run these tests.

The GPU's DMA ring RPTR is found to be at index 3 (it should be at
index 4 after consuming all 4 32-bit words, when starting at index 0).
Since the write-back of GPU's RPTR is successful, the DMA from
GPU to system RAM works.

Contents of some registers, before and after running the DMA test:

DMA_STATUS: 0x44c83d57, 0x44c83156 (IDLE bit is off in the after
status)
GRBM_STATUS: 0x3828, 0x3828
SRBM_STATUS: 0x200000c0, 0x200000c0

If the DMA WRITE(2) cmd is replaced with a TRAP(7), the DMA
RPTR does not even move a single step - after the timeout, it is
found to be still at 0. And the IDLE status is found to be OFF.
The expected interrupt isn't generated.

If, instead, 4 NOPs(15) are sent, the DMA ring is again found to be
stuck at RPTR=3 with IDLE status as OFF. It seems to have an
affinity towards the 3rd position from the start.

I also ran the CP ring test with a MEM_WRITE operation instead of the
default SET_CONFIG_REG op. The test succeeds, thus proving that
the CP ring can indeed DMA into the system RAM at the lowest perf
profile.

Does this mean that the GPU doesn't support running DMA ring at the
lowest perf profile (157Mhz/200MHz)? I do still believe that this
situation might be a result of faulty/missing programming on my part,
though I am not sure what exactly it is that is at fault or is missing.

The machine is a kvm-vfio-enabled VM; the current ArchLinux ISO fails
to initialize the passthru device (-22 from radeon_device_init).

Thanks,
Amol


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