[bug report] drm/amdkfd: Add KFD support for soc21 v3

[Dan Carpenter]

Hello Mukul Joshi,

The patch cc009e613de6: "drm/amdkfd: Add KFD support for soc21 v3"
from Apr 26, 2022, leads to the following Smatch static checker
warning:

	drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c:205 add_queue_mes()
	warn: unsigned 'queue_input.queue_type' is never less than zero.

drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.c
    173 static int add_queue_mes(struct device_queue_manager *dqm, struct queue *q,
    174                          struct qcm_process_device *qpd)
    175 {
    176         struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev;
    177         struct kfd_process_device *pdd = qpd_to_pdd(qpd);
    178         struct mes_add_queue_input queue_input;
    179         int r;
    180 
    181         if (dqm->is_hws_hang)
    182                 return -EIO;
    183 
    184         memset(&queue_input, 0x0, sizeof(struct mes_add_queue_input));
    185         queue_input.process_id = qpd->pqm->process->pasid;
    186         queue_input.page_table_base_addr =  qpd->page_table_base;
    187         queue_input.process_va_start = 0;
    188         queue_input.process_va_end = adev->vm_manager.max_pfn - 1;
    189         /* MES unit for quantum is 100ns */
    190         queue_input.process_quantum = KFD_MES_PROCESS_QUANTUM;  /* Equivalent to 10ms. */
    191         queue_input.process_context_addr = pdd->proc_ctx_gpu_addr;
    192         queue_input.gang_quantum = KFD_MES_GANG_QUANTUM; /* Equivalent to 1ms */
    193         queue_input.gang_context_addr = q->gang_ctx_gpu_addr;
    194         queue_input.inprocess_gang_priority = q->properties.priority;
    195         queue_input.gang_global_priority_level =
    196                                         AMDGPU_MES_PRIORITY_LEVEL_NORMAL;
    197         queue_input.doorbell_offset = q->properties.doorbell_off;
    198         queue_input.mqd_addr = q->gart_mqd_addr;
    199         queue_input.wptr_addr = (uint64_t)q->properties.write_ptr;
    200         queue_input.paging = false;
    201         queue_input.tba_addr = qpd->tba_addr;
    202         queue_input.tma_addr = qpd->tma_addr;
    203 
    204         queue_input.queue_type = convert_to_mes_queue_type(q->properties.type);
--> 205         if (queue_input.queue_type < 0) {

This is a u32 so it can't be negative.  Some convert_to_mes_queue_type()
functions return -1 and some return -EINVAL.

    206                 pr_err("Queue type not supported with MES, queue:%d\n",
    207                                 q->properties.type);
    208                 return -EINVAL;
    209         }
    210 
    211         if (q->gws) {
    212                 queue_input.gws_base = 0;
    213                 queue_input.gws_size = qpd->num_gws;
    214         }
    215 
    216         amdgpu_mes_lock(&adev->mes);
    217         r = adev->mes.funcs->add_hw_queue(&adev->mes, &queue_input);
    218         amdgpu_mes_unlock(&adev->mes);
    219         if (r) {
    220                 pr_err("failed to add hardware queue to MES, doorbell=0x%x\n",
    221                         q->properties.doorbell_off);
    222                 pr_err("MES might be in unrecoverable state, issue a GPU reset\n");
    223                 kfd_hws_hang(dqm);
    224 }

regards,
dan carpenter