[PATCH] drm/amdgpu: Clean up of initializing doorbells for gfx_v9 and gfx_v10

[Alex Deucher]

Applied.  Thanks!

Alex

On Mon, May 16, 2022 at 8:01 AM <ricetons at gmail.com> wrote:
>
> From: Haohui Mai <ricetons at gmail.com>
>
> Clean up redundant, copy-paste code blocks during the intialization of
> the doorbells in mqd_init().
>
> Signed-off-by: Haohui Mai <ricetons at gmail.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 17 -----------------
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 17 -----------------
>  2 files changed, 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 4b66b9c93754..12f63d6aab12 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6919,23 +6919,6 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
>         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
>         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
>
> -       tmp = 0;
> -       /* enable the doorbell if requested */
> -       if (prop->use_doorbell) {
> -               tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                               DOORBELL_OFFSET, prop->doorbell_index);
> -
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                   DOORBELL_EN, 1);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                   DOORBELL_SOURCE, 0);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                   DOORBELL_HIT, 0);
> -       }
> -
> -       mqd->cp_hqd_pq_doorbell_control = tmp;
> -
>         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
>         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 83639b5ea6a9..f49a2dd89ee7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3535,23 +3535,6 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
>         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
>
> -       tmp = 0;
> -       /* enable the doorbell if requested */
> -       if (ring->use_doorbell) {
> -               tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                               DOORBELL_OFFSET, ring->doorbell_index);
> -
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                        DOORBELL_EN, 1);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                        DOORBELL_SOURCE, 0);
> -               tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
> -                                        DOORBELL_HIT, 0);
> -       }
> -
> -       mqd->cp_hqd_pq_doorbell_control = tmp;
> -
>         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
>         ring->wptr = 0;
>         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
> --
> 2.25.1
>