[PATCH] drm/amdgpu: Set CP_HQD_PQ_CONTROL_RPTR_BLOCK_SIZE correctly in gfx_v8-v11.

[Alex Deucher]

On Tue, May 17, 2022 at 2:06 AM <ricetons at gmail.com> wrote:
>
> From: Haohui Mai <ricetons at gmail.com>
>
> Remove the accidental shifts on the values of RPTR_BLOCK_SIZE in gfx_v8-v11.
> The bug essentially always programs the corresponding fields to zero
> instead of the correct value.

The hardware clamps values below 5 to 5.  Updated that in the commit
message and applied.

Thanks,

Alex


>
> Signed-off-by: Haohui Mai <ricetons at gmail.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c  | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 2 +-
>  4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 12f63d6aab12..dd8f4344eeb8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -6898,7 +6898,7 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
>                             (order_base_2(prop->queue_size / 4) - 1));
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> -                           ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
> +                           (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
>  #ifdef __BIG_ENDIAN
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 8a1bec70c719..82c98e59a13e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4082,7 +4082,7 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
>                             (order_base_2(prop->queue_size / 4) - 1));
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> -                           ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
> +                           (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 90f64219d291..fb9302910742 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4490,7 +4490,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
>                             (order_base_2(ring->ring_size / 4) - 1));
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> -                       ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
> +                       (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
>  #ifdef __BIG_ENDIAN
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index f49a2dd89ee7..f12ae6e2359a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3514,7 +3514,7 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
>                             (order_base_2(ring->ring_size / 4) - 1));
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
> -                       ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
> +                       (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
>  #ifdef __BIG_ENDIAN
>         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
>  #endif
> --
> 2.25.1
>