[PATCH] drm/amd/pm: suppress compile warnings about possible unaligned accesses
Alex Deucher
alexdeucher at gmail.com
Tue May 31 15:37:36 UTC 2022
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
On Mon, May 30, 2022 at 2:10 AM Evan Quan <evan.quan at amd.com> wrote:
>
> Suppress the following compile warnings:
> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_pptable.h:163:17:
> warning: field smc_pptable within 'struct smu_11_0_powerplay_table' is
> less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_powerplay_table'
> being packed, which can lead to unaligned accesses [-Wunaligned-access]
> PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
> ^
> 1 warning generated.
> --
> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v11_0_7_pptable.h:193:17:
> warning: field smc_pptable within 'struct smu_11_0_7_powerplay_table' is
> less aligned than 'PPTable_t' and is usually due to 'struct smu_11_0_7_powerplay_table'
> being packed, which can lead to unaligned accesses [-Wunaligned-access]
> PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
> ^
> 1 warning generated.
> --
> >> drivers/gpu/drm/amd/amdgpu/../pm/swsmu/inc/smu_v13_0_pptable.h:161:12:
> warning: field smc_pptable within 'struct smu_13_0_powerplay_table' is less aligned than
> 'PPTable_t' and is usually due to 'struct smu_13_0_powerplay_table' being packed, which
> can lead to unaligned accesses [-Wunaligned-access]
>
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> Change-Id: I855062e987effd563ccc09336caad75f02751bb6
> ---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h | 9 ++++++---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h | 9 ++++++---
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h | 5 ++++-
> drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h | 10 +++++++---
> 4 files changed, 23 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> index 247c6e9632ba..1cb399dbc7cc 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h
> @@ -22,6 +22,7 @@
> #ifndef SMU_11_0_7_PPTABLE_H
> #define SMU_11_0_7_PPTABLE_H
>
> +#pragma pack(push, 1)
>
> #define SMU_11_0_7_TABLE_FORMAT_REVISION 15
>
> @@ -139,7 +140,7 @@ struct smu_11_0_7_overdrive_table
> uint32_t max[SMU_11_0_7_MAX_ODSETTING]; //default maximum settings
> uint32_t min[SMU_11_0_7_MAX_ODSETTING]; //default minimum settings
> int16_t pm_setting[SMU_11_0_7_MAX_PMSETTING]; //Optimized power mode feature settings
> -} __attribute__((packed));
> +};
>
> enum SMU_11_0_7_PPCLOCK_ID {
> SMU_11_0_7_PPCLOCK_GFXCLK = 0,
> @@ -166,7 +167,7 @@ struct smu_11_0_7_power_saving_clock_table
> uint32_t count; //power_saving_clock_count = SMU_11_0_7_PPCLOCK_COUNT
> uint32_t max[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
> uint32_t min[SMU_11_0_7_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
> -} __attribute__((packed));
> +};
>
> struct smu_11_0_7_powerplay_table
> {
> @@ -191,6 +192,8 @@ struct smu_11_0_7_powerplay_table
> struct smu_11_0_7_overdrive_table overdrive_table;
>
> PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
> -} __attribute__((packed));
> +};
> +
> +#pragma pack(pop)
>
> #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> index 7a63cf8e85ed..0116e3d04fad 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h
> @@ -22,6 +22,7 @@
> #ifndef SMU_11_0_PPTABLE_H
> #define SMU_11_0_PPTABLE_H
>
> +#pragma pack(push, 1)
>
> #define SMU_11_0_TABLE_FORMAT_REVISION 12
>
> @@ -109,7 +110,7 @@ struct smu_11_0_overdrive_table
> uint8_t cap[SMU_11_0_MAX_ODFEATURE]; //OD feature support flags
> uint32_t max[SMU_11_0_MAX_ODSETTING]; //default maximum settings
> uint32_t min[SMU_11_0_MAX_ODSETTING]; //default minimum settings
> -} __attribute__((packed));
> +};
>
> enum SMU_11_0_PPCLOCK_ID {
> SMU_11_0_PPCLOCK_GFXCLK = 0,
> @@ -133,7 +134,7 @@ struct smu_11_0_power_saving_clock_table
> uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
> uint32_t max[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
> uint32_t min[SMU_11_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
> -} __attribute__((packed));
> +};
>
> struct smu_11_0_powerplay_table
> {
> @@ -162,6 +163,8 @@ struct smu_11_0_powerplay_table
> #ifndef SMU_11_0_PARTIAL_PPTABLE
> PPTable_t smc_pptable; //PPTable_t in smu11_driver_if.h
> #endif
> -} __attribute__((packed));
> +};
> +
> +#pragma pack(pop)
>
> #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> index 3f29f4327378..478862ded0bd 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h
> @@ -22,6 +22,8 @@
> #ifndef SMU_13_0_7_PPTABLE_H
> #define SMU_13_0_7_PPTABLE_H
>
> +#pragma pack(push, 1)
> +
> #define SMU_13_0_7_TABLE_FORMAT_REVISION 15
>
> //// POWERPLAYTABLE::ulPlatformCaps
> @@ -194,7 +196,8 @@ struct smu_13_0_7_powerplay_table
> struct smu_13_0_7_overdrive_table overdrive_table;
> uint8_t padding1;
> PPTable_t smc_pptable; //PPTable_t in driver_if.h
> -} __attribute__((packed));
> +};
>
> +#pragma pack(pop)
>
> #endif
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h
> index 1f311396b706..043307485528 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h
> +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_pptable.h
> @@ -22,6 +22,8 @@
> #ifndef SMU_13_0_PPTABLE_H
> #define SMU_13_0_PPTABLE_H
>
> +#pragma pack(push, 1)
> +
> #define SMU_13_0_TABLE_FORMAT_REVISION 1
>
> //// POWERPLAYTABLE::ulPlatformCaps
> @@ -109,7 +111,7 @@ struct smu_13_0_overdrive_table {
> uint8_t cap[SMU_13_0_MAX_ODFEATURE]; //OD feature support flags
> uint32_t max[SMU_13_0_MAX_ODSETTING]; //default maximum settings
> uint32_t min[SMU_13_0_MAX_ODSETTING]; //default minimum settings
> -} __attribute__((packed));
> +};
>
> enum SMU_13_0_PPCLOCK_ID {
> SMU_13_0_PPCLOCK_GFXCLK = 0,
> @@ -132,7 +134,7 @@ struct smu_13_0_power_saving_clock_table {
> uint32_t count; //power_saving_clock_count = SMU_11_0_PPCLOCK_COUNT
> uint32_t max[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Maximum array In MHz
> uint32_t min[SMU_13_0_MAX_PPCLOCK]; //PowerSavingClock Mode Clock Minimum array In MHz
> -} __attribute__((packed));
> +};
>
> struct smu_13_0_powerplay_table {
> struct atom_common_table_header header;
> @@ -160,6 +162,8 @@ struct smu_13_0_powerplay_table {
> #ifndef SMU_13_0_PARTIAL_PPTABLE
> PPTable_t smc_pptable; //PPTable_t in driver_if.h
> #endif
> -} __attribute__((packed));
> +};
> +
> +#pragma pack(pop)
>
> #endif
> --
> 2.29.0
>
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