[PATCH] drm/amdkfd: correct the cache info for gfx1036

[Zhang, Yifan]

[Public]

This patch is

Reviewed-by: Yifan Zhang <yifan1.zhang at amd.com>

From: Zhang, Jesse(Jie) <Jesse.Zhang at amd.com>
Sent: Tuesday, October 11, 2022 1:23 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Yifan <Yifan1.Zhang at amd.com>; Kuehling, Felix <Felix.Kuehling at amd.com>
Subject: RE: [PATCH] drm/amdkfd: correct the cache info for gfx1036


[AMD Official Use Only - General]



   correct the cache information for gfx1036



    Signed-off-by: Yifan Zhang yifan1.zhang at amd.com<mailto:yifan1.zhang at amd.com>



    Signed-off-by: jie1zhan jesse.zhang at amd.com<mailto:jesse.zhang at amd.com>

    Change-Id: I60e754737057c144e69a6511ba6ddfca472ca7a1



diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

index 477a30981c1b..d25ac9cbe5b2 100644

--- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

+++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c

@@ -795,6 +795,54 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {

        },

};



+static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {

+       {

+               /* TCP L1 Cache per CU */

+               .cache_size = 16,

+               .cache_level = 1,

+               .flags = (CRAT_CACHE_FLAGS_ENABLED |

+                               CRAT_CACHE_FLAGS_DATA_CACHE |

+                               CRAT_CACHE_FLAGS_SIMD_CACHE),

+               .num_cu_shared = 1,

+       },

+       {

+               /* Scalar L1 Instruction Cache per SQC */

+               .cache_size = 32,

+               .cache_level = 1,

+               .flags = (CRAT_CACHE_FLAGS_ENABLED |

+                               CRAT_CACHE_FLAGS_INST_CACHE |

+                               CRAT_CACHE_FLAGS_SIMD_CACHE),

+               .num_cu_shared = 2,

+       },

+       {

+               /* Scalar L1 Data Cache per SQC */

+               .cache_size = 16,

+               .cache_level = 1,

+               .flags = (CRAT_CACHE_FLAGS_ENABLED |

+                               CRAT_CACHE_FLAGS_DATA_CACHE |

+                               CRAT_CACHE_FLAGS_SIMD_CACHE),

+               .num_cu_shared = 2,

+       },

+       {

+               /* GL1 Data Cache per SA */

+               .cache_size = 128,

+               .cache_level = 1,

+               .flags = (CRAT_CACHE_FLAGS_ENABLED |

+                               CRAT_CACHE_FLAGS_DATA_CACHE |

+                               CRAT_CACHE_FLAGS_SIMD_CACHE),

+               .num_cu_shared = 2,

+       },

+       {

+               /* L2 Data Cache per GPU (Total Tex Cache) */

+               .cache_size = 256,

+               .cache_level = 2,

+               .flags = (CRAT_CACHE_FLAGS_ENABLED |

+                               CRAT_CACHE_FLAGS_DATA_CACHE |

+                               CRAT_CACHE_FLAGS_SIMD_CACHE),

+               .num_cu_shared = 2,

+       },

+};

+

static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,

                struct crat_subtype_computeunit *cu)

{

@@ -1514,11 +1562,14 @@ static int kfd_fill_gpu_cache_info(struct kfd_dev *kdev,

                        num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);

                        break;

                case IP_VERSION(10, 3, 3):

-               case IP_VERSION(10, 3, 6): /* TODO: Double check these on production silicon */

                case IP_VERSION(10, 3, 7): /* TODO: Double check these on production silicon */

                        pcache_info = yellow_carp_cache_info;

                        num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);

                        break;

+               case IP_VERSION(10, 3, 6):

+                       pcache_info = gc_10_3_6_cache_info;

+                       num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);

+                       break;

                case IP_VERSION(11, 0, 0):
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