[PATCH v3] drm/amdgpu: set vm_update_mode=0 as default for Sienna Cichlid in SRIOV case

[Felix Kuehling]

Am 2022-10-12 um 09:20 schrieb Danijel Slivka:
> For asic with VF MMIO access protection avoid using CPU for VM table updates.
> CPU pagetable updates have issues with HDP flush as VF MMIO access protection
> blocks write to mmBIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register
> during sriov runtime.
>
> v3: introduce virtualization capability flag AMDGPU_VF_MMIO_ACCESS_PROTECT
> which indicates that VF MMIO write access is not allowed in sriov runtime
>
> Signed-off-by: Danijel Slivka <danijel.slivka at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 6 ++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 5 +++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c   | 6 +++++-
>   3 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> index e4af40b9a8aa..9c765b04aae3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
> @@ -726,6 +726,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
>   			adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
>   	}
>   
> +	if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID)
> +		/* VF MMIO access (except mailbox range) from CPU
> +		 * will be blocked during sriov runtime
> +		 */
> +		adev->virt.caps |= AMDGPU_VF_MMIO_ACCESS_PROTECT;
> +
>   	/* we have the ability to check now */
>   	if (amdgpu_sriov_vf(adev)) {
>   		switch (adev->asic_type) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index d94c31e68a14..fffc224ff03d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -31,6 +31,7 @@
>   #define AMDGPU_SRIOV_CAPS_IS_VF        (1 << 2) /* this GPU is a virtual function */
>   #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass through for VM */
>   #define AMDGPU_SRIOV_CAPS_RUNTIME      (1 << 4) /* is out of full access mode */
> +#define AMDGPU_VF_MMIO_ACCESS_PROTECT  (1 << 5) /* MMIO write access is not allowed in sriov runtime */
>   
>   /* flags for indirect register access path supported by rlcg for sriov */
>   #define AMDGPU_RLCG_GC_WRITE_LEGACY    (0x8 << 28)
> @@ -297,6 +298,10 @@ struct amdgpu_video_codec_info;
>   #define amdgpu_passthrough(adev) \
>   ((adev)->virt.caps & AMDGPU_PASSTHROUGH_MODE)
>   
> +#define amdgpu_sriov_vf_mmio_access_protection(adev) \
> +(amdgpu_sriov_vf((adev)) && \
> +	((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT))

The ACCESS_PROTECT flag is only set for VFs in 
amdgpu_detect_virtualization. So I think you can remove amdgpu_sriov_vf 
check here. With that fixed, the patch is

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> +
>   static inline bool is_virtual_machine(void)
>   {
>   #if defined(CONFIG_X86)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 83b0c5d86e48..2291aa14d888 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2338,7 +2338,11 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev)
>   	 */
>   #ifdef CONFIG_X86_64
>   	if (amdgpu_vm_update_mode == -1) {
> -		if (amdgpu_gmc_vram_full_visible(&adev->gmc))
> +		/* For asic with VF MMIO access protection
> +		 * avoid using CPU for VM table updates
> +		 */
> +		if (amdgpu_gmc_vram_full_visible(&adev->gmc) &&
> +		    !amdgpu_sriov_vf_mmio_access_protection(adev))
>   			adev->vm_manager.vm_update_mode =
>   				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
>   		else