[PATCH v2] drm/amdgpu: Skip program gfxhub_v3_0_3 system aperture registers under SRIOV

[Alex Deucher]

On Tue, Oct 25, 2022 at 4:29 AM Yifan Zha <Yifan.Zha at amd.com> wrote:
>
> [Why]
> gfxhub_v3_0_3 system aperture registers are removed from RLCG register access range.
>
> [How]
> Skip access gfxhub_v3_0_3 system aperture registers under SRIOV VF.
> These registers will be programmed on host side.
>
> Signed-off-by: Yifan Zha <Yifan.Zha at amd.com>

Series is:
Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> index 5d3fffd4929f..716ae6f2aefe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.c
> @@ -154,6 +154,9 @@ static void gfxhub_v3_0_3_init_system_aperture_regs(struct amdgpu_device *adev)
>  {
>         uint64_t value;
>
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +
>         /* Disable AGP. */
>         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_BASE, 0);
>         WREG32_SOC15(GC, 0, regGCMC_VM_AGP_TOP, 0);
> --
> 2.25.1
>