[PATCH 4/5] drm/amdgpu: MCBP based on DRM scheduler (v8)

[Michel Dänzer]

On 2022-10-18 11:08, jiadong.zhu at amd.com wrote:
> From: "Jiadong.Zhu" <Jiadong.Zhu at amd.com>
> 
> Trigger Mid-Command Buffer Preemption according to the priority of the software
> rings and the hw fence signalling condition.
> 
> The muxer saves the locations of the indirect buffer frames from the software
> ring together with the fence sequence number in its fifo queue, and pops out
> those records when the fences are signalled. The locations are used to resubmit
> packages in preemption scenarios by coping the chunks from the software ring.
> 
> v2: Update comment style.
> v3: Fix conflict caused by previous modifications.
> v4: Remove unnecessary prints.
> v5: Fix corner cases for resubmission cases.
> v6: Refactor functions for resubmission, calling fence_process in irq handler.
> v7: Solve conflict for removing amdgpu_sw_ring.c.
> v8: Add time threshold to judge if preemption request is needed.
> 
> Cc: Christian Koenig <Christian.Koenig at amd.com>
> Cc: Luben Tuikov <Luben.Tuikov at amd.com>
> Cc: Andrey Grodzovsky <Andrey.Grodzovsky at amd.com>
> Cc: Michel Dänzer <michel at daenzer.net>
> Signed-off-by: Jiadong.Zhu <Jiadong.Zhu at amd.com>
> Acked-by: Luben Tuikov <luben.tuikov at amd.com>
> Acked-by: Huang Rui <ray.huang at amd.com>

[...]

> +/* Trigger Mid-Command Buffer Preemption (MCBP) and find if we need to resubmit. */
> +int amdgpu_mcbp_trigger_preempt(struct amdgpu_ring_mux *mux)
> +{
> +	int r;
> +
> +	spin_lock(&mux->lock);
> +	mux->pending_trailing_fence_signaled = true;
> +	r = amdgpu_ring_preempt_ib(mux->real_ring);
> +	spin_unlock(&mux->lock);
> +	return r;
> +}

AFAICT amdgpu_mcbp_trigger_preempt is used only in this file, so it should be declared static.

(I didn't audit the other new functions added by this series for this, just happened to notice this one)


-- 
Earthling Michel Dänzer            |                  https://redhat.com
Libre software enthusiast          |         Mesa and Xwayland developer