[PATCH] drm/amdgpu: Update PTE flags with TF enabled

[Felix Kuehling]

Am 2022-09-13 um 18:16 schrieb Mukul Joshi:
> This patch updates the PTE flags when translate further (TF) is
> enabled:
> - With translate_further enabled, invalid PTEs can be 0. Reading
>    consecutive invalid PTEs as 0 is considered a fault. To prevent
>    this, ensure invalid PTEs have at least 1 bit set.
> - The current invalid PTE flags settings to translate a retry fault
>    into a no-retry fault, doesn't work with TF enabled. As a result,
>    update invalid PTE flags settings which works for both TF enabled
>    and disabled case.
>
> Fixes: 2abf2573b1c69 ("drm/amdgpu: Enable translate_further to extend UTCL2 reach")
> Signed-off-by: Mukul Joshi <mukul.joshi at amd.com>

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c  | 7 +++++--
>   2 files changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 59cac347baa3..690fd4f639f1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2484,8 +2484,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
>   		/* Intentionally setting invalid PTE flag
>   		 * combination to force a no-retry-fault
>   		 */
> -		flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
> -			AMDGPU_PTE_TF;
> +		flags = AMDGPU_PTE_SNOOPED | AMDGPU_PTE_PRT;
>   		value = 0;
>   	} else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
>   		/* Redirect the access to the dummy page */
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 4603653916f5..67ca16a8027c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -1103,10 +1103,13 @@ static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
>   			*flags |= AMDGPU_PDE_BFS(0x9);
>   
>   	} else if (level == AMDGPU_VM_PDB0) {
> -		if (*flags & AMDGPU_PDE_PTE)
> +		if (*flags & AMDGPU_PDE_PTE) {
>   			*flags &= ~AMDGPU_PDE_PTE;
> -		else
> +			if (!(*flags & AMDGPU_PTE_VALID))
> +				*addr |= 1 << PAGE_SHIFT;
> +		} else {
>   			*flags |= AMDGPU_PTE_TF;
> +		}
>   	}
>   }
>