[PATCH] gpu: dc: fix enum conversion in display_mode_vba
Zeng Heng
zengheng4 at huawei.com
Thu Sep 22 09:16:41 UTC 2022
I just correct the subject line and resend the patch mail.
Please refer to:
[PATCH resend v2] drm/amdgpu: fix enum conversion in display_mode_vba
On 2022/9/19 15:44, Christian König wrote:
> Am 19.09.22 um 03:41 schrieb Zeng Heng:
>> Fix below compile warning when open enum-conversion
>> option check (compiled with -Wenum-conversion):
>>
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:
>>
>> In function ‘dml20_ModeSupportAndSystemConfigurationFull’:
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:3900:44:
>>
>> error: implicit conversion from ‘enum <anonymous>’ to ‘enum
>> odm_combine_mode’ [-Werror=enum-conversion]
>> 3900 | locals->ODMCombineEnablePerState[i][k] = false;
>> | ^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:3904:46:
>>
>> error: implicit conversion from ‘enum <anonymous>’ to ‘enum
>> odm_combine_mode’ [-Werror=enum-conversion]
>> 3904 | locals->ODMCombineEnablePerState[i][k] = true;
>> | ^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:3907:46:
>>
>> error: implicit conversion from ‘enum <anonymous>’ to ‘enum
>> odm_combine_mode’ [-Werror=enum-conversion]
>> 3907 | locals->ODMCombineEnablePerState[i][k] = true;
>> | ^
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.c:3960:45:
>>
>> error: implicit conversion from ‘enum <anonymous>’ to ‘enum
>> odm_combine_mode’ [-Werror=enum-conversion]
>> 3960 | locals->ODMCombineEnablePerState[i][k] = false;
>>
>> Use the proper value from the right enumerated type,
>> dm_odm_combine_mode_disabled & dm_odm_combine_mode_2to1,
>> so there is no more implicit conversion.
>>
>> The numerical values of dm_odm_combine_mode_disabled
>> & false and dm_odm_combine_mode_2to1 & true
>> happen to be the same, so there is no change in
>> behavior.
>
> In the subject line the correct prefix is "drm/amdgpu: ....", but
> apart from that looks good to me as well.
>
> But our DC team has to take a closer look.
>
> Thanks,
> Christian.
>
>>
>> Signed-off-by: Zeng Heng <zengheng4 at huawei.com>
>> ---
>> .../amd/display/dc/dml/dcn20/display_mode_vba_20.c | 8 ++++----
>> .../amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 10 +++++-----
>> .../amd/display/dc/dml/dcn21/display_mode_vba_21.c | 12 ++++++------
>> 3 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> index d3b5b6fedf04..6266b0788387 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
>> @@ -3897,14 +3897,14 @@ void
>> dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode_l
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine =
>> mode_lib->vba.PixelClock[k] / 2
>> * (1 +
>> mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
>> if (mode_lib->vba.ODMCapability) {
>> if
>> (locals->PlaneRequiredDISPCLKWithoutODMCombine >
>> mode_lib->vba.MaxDispclkRoundedDownToDFSGranularity) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> } else if (locals->HActive[k] >
>> DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> }
>> }
>> @@ -3957,7 +3957,7 @@ void
>> dml20_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode_l
>> locals->RequiredDISPCLK[i][j] = 0.0;
>> locals->DISPCLK_DPPCLK_Support[i][j] = true;
>> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes
>> - 1; k++) {
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> if (locals->SwathWidthYSingleDPP[k] <=
>> locals->MaximumSwathWidth[k]) {
>> locals->NoOfDPP[i][j][k] = 1;
>> locals->RequiredDPPCLK[i][j][k] =
>> locals->MinDPPCLKUsingSingleDPP[k]
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
>> index edd098c7eb92..989d83ee3842 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
>> @@ -4008,17 +4008,17 @@ void
>> dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine =
>> mode_lib->vba.PixelClock[k] / 2
>> * (1 +
>> mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
>> if (mode_lib->vba.ODMCapability) {
>> if
>> (locals->PlaneRequiredDISPCLKWithoutODMCombine >
>> MaxMaxDispclkRoundedDown) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> } else if (locals->DSCEnabled[k] &&
>> (locals->HActive[k] > DCN20_MAX_DSC_IMAGE_WIDTH)) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> } else if (locals->HActive[k] >
>> DCN20_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> }
>> }
>> @@ -4071,7 +4071,7 @@ void
>> dml20v2_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode
>> locals->RequiredDISPCLK[i][j] = 0.0;
>> locals->DISPCLK_DPPCLK_Support[i][j] = true;
>> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes
>> - 1; k++) {
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> if (locals->SwathWidthYSingleDPP[k] <=
>> locals->MaximumSwathWidth[k]) {
>> locals->NoOfDPP[i][j][k] = 1;
>> locals->RequiredDPPCLK[i][j][k] =
>> locals->MinDPPCLKUsingSingleDPP[k]
>> diff --git
>> a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
>> b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
>> index d40d32e380f4..f15e82492381 100644
>> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
>> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
>> @@ -4102,17 +4102,17 @@ void
>> dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode_l
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine =
>> mode_lib->vba.PixelClock[k] / 2
>> * (1 +
>> mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100.0);
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithoutODMCombine;
>> if (mode_lib->vba.ODMCapability) {
>> if
>> (locals->PlaneRequiredDISPCLKWithoutODMCombine >
>> MaxMaxDispclkRoundedDown) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> } else if (locals->DSCEnabled[k] &&
>> (locals->HActive[k] > DCN21_MAX_DSC_IMAGE_WIDTH)) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> } else if (locals->HActive[k] >
>> DCN21_MAX_420_IMAGE_WIDTH && locals->OutputFormat[k] == dm_420) {
>> - locals->ODMCombineEnablePerState[i][k] = true;
>> + locals->ODMCombineEnablePerState[i][k] = dm_odm_combine_mode_2to1;
>> mode_lib->vba.PlaneRequiredDISPCLK =
>> mode_lib->vba.PlaneRequiredDISPCLKWithODMCombine;
>> }
>> }
>> @@ -4165,7 +4165,7 @@ void
>> dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode_l
>> locals->RequiredDISPCLK[i][j] = 0.0;
>> locals->DISPCLK_DPPCLK_Support[i][j] = true;
>> for (k = 0; k <= mode_lib->vba.NumberOfActivePlanes
>> - 1; k++) {
>> - locals->ODMCombineEnablePerState[i][k] = false;
>> + locals->ODMCombineEnablePerState[i][k] =
>> dm_odm_combine_mode_disabled;
>> if (locals->SwathWidthYSingleDPP[k] <=
>> locals->MaximumSwathWidth[k]) {
>> locals->NoOfDPP[i][j][k] = 1;
>> locals->RequiredDPPCLK[i][j][k] =
>> locals->MinDPPCLKUsingSingleDPP[k]
>> @@ -5230,7 +5230,7 @@ void
>> dml21_ModeSupportAndSystemConfigurationFull(struct display_mode_lib
>> *mode_l
>> mode_lib->vba.ODMCombineEnabled[k] =
>> locals->ODMCombineEnablePerState[mode_lib->vba.VoltageLevel][k];
>> } else {
>> - mode_lib->vba.ODMCombineEnabled[k] = false;
>> + mode_lib->vba.ODMCombineEnabled[k] =
>> dm_odm_combine_mode_disabled;
>> }
>> mode_lib->vba.DSCEnabled[k] =
>> locals->RequiresDSC[mode_lib->vba.VoltageLevel][k];
>
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