[PATCH v2] drm/amd/display: Add logging when DP link training Channel EQ is Successful

[Srinivasan Shanmugam]

Log when Channel Equalization is successful,
and DP link training completed.

Cc: Aurabindo Pillai <aurabindo.pillai at amd.com>
Cc: Fangzhi Zuo <Jerry.Zuo at amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam at amd.com>
---

v2:

 - For consistency of the printed messages, dropped  %s for both the
   lines (Aurabindo)
 - For 128b/132b, moved the statements after EQ interlane alignment
   is done.

 .../display/dc/link/protocols/link_dp_training_128b_132b.c   | 2 ++
 .../amd/display/dc/link/protocols/link_dp_training_8b_10b.c  | 5 ++++-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
index 23d380f09a21..f7d62b79008f 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_128b_132b.c
@@ -136,6 +136,8 @@ static enum link_training_result dp_perform_128b_132b_channel_eq_done_sequence(
 			result = LINK_TRAINING_ABORT;
 		} else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) {
 			/* pass */
+			DC_LOG_HW_LINK_TRAINING("Channel EQ done.\n");
+			DC_LOG_HW_LINK_TRAINING("DP 128b/132b Link Training successful\n");
 			break;
 		} else if (wait_time >= lt_settings->eq_wait_time_limit) {
 			result = DP_128b_132b_CHANNEL_EQ_DONE_TIMEOUT;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 14b98e096d39..e10b2db87001 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -337,8 +337,11 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(
 		/* 6. check CHEQ done*/
 		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
 				dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
-				dp_is_interlane_aligned(dpcd_lane_status_updated))
+				dp_is_interlane_aligned(dpcd_lane_status_updated)) {
+			DC_LOG_HW_LINK_TRAINING("Channel EQ done.\n");
+			DC_LOG_HW_LINK_TRAINING("DP 8b/10b Link Training successful\n");
 			return LINK_TRAINING_SUCCESS;
+		}
 
 		/* 7. update VS/PE/PC2 in lt_settings*/
 		dp_decide_lane_settings(lt_settings, dpcd_lane_adjust,
-- 
2.25.1