[PATCH] drm/amd/amdgpu: Fix style errors in amdgpu_drv.c & amdgpu_device.c
Christian König
christian.koenig at amd.com
Wed Apr 19 11:45:21 UTC 2023
Am 19.04.23 um 13:42 schrieb Srinivasan Shanmugam:
> Fix following checkpatch style errors in amdgpu_drv.c &
> amdgpu_device.c
>
> ERROR: exactly one space required after that #ifdef
> ERROR: spaces required around that '+=' (ctx:WxV)
> ERROR: space required before the open brace '{'
> ERROR: spaces required around that '||' (ctx:VxE)
> ERROR: space prohibited before that close parenthesis ')'
> ERROR: space required before the open parenthesis '('
> ERROR: space required before the open brace '{'
> ERROR: code indent should use tabs where possible
>
> Cc: Christian König <christian.koenig at amd.com>
> Cc: Alex Deucher <alexander.deucher at amd.com>
> Cc: Mario Limonciello <mario.limonciello at amd.com>
> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 65 +++++++++++-----------
> drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +-
> 2 files changed, 34 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 3e854cd8d22e..e536886f6d42 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -997,7 +997,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
> if (array_size % 3)
> return;
>
> - for (i = 0; i < array_size; i +=3) {
> + for (i = 0; i < array_size; i += 3) {
> reg = registers[i + 0];
> and_mask = registers[i + 1];
> or_mask = registers[i + 2];
> @@ -1546,7 +1546,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev)
> dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
> amdgpu_sched_jobs);
> amdgpu_sched_jobs = 4;
> - } else if (!is_power_of_2(amdgpu_sched_jobs)){
> + } else if (!is_power_of_2(amdgpu_sched_jobs)) {
> dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
> amdgpu_sched_jobs);
> amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
> @@ -2758,8 +2758,9 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev)
> DRM_ERROR("enable mgpu fan boost failed (%d).\n", r);
>
> /* For passthrough configuration on arcturus and aldebaran, enable special handling SBR */
> - if (amdgpu_passthrough(adev) && ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1)||
> - adev->asic_type == CHIP_ALDEBARAN ))
> + if (amdgpu_passthrough(adev) &&
> + ((adev->asic_type == CHIP_ARCTURUS && adev->gmc.xgmi.num_physical_nodes > 1) ||
> + adev->asic_type == CHIP_ALDEBARAN))
> amdgpu_dpm_handle_passthrough_sbr(adev, true);
>
> if (adev->gmc.xgmi.num_physical_nodes > 1) {
> @@ -3088,7 +3089,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev)
> }
> adev->ip_blocks[i].status.hw = false;
> /* handle putting the SMC in the appropriate state */
> - if(!amdgpu_sriov_vf(adev)){
> + if (!amdgpu_sriov_vf(adev)) {
> if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
> r = amdgpu_dpm_set_mp1_state(adev, adev->mp1_state);
> if (r) {
> @@ -4035,7 +4036,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
>
> /* disable all interrupts */
> amdgpu_irq_disable_all(adev);
> - if (adev->mode_info.mode_config_initialized){
> + if (adev->mode_info.mode_config_initialized) {
> if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev)))
> drm_helper_force_disable_all(adev_to_drm(adev));
> else
> @@ -4698,42 +4699,42 @@ bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev)
>
> int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
> {
> - u32 i;
> - int ret = 0;
> + u32 i;
> + int ret = 0;
>
> - amdgpu_atombios_scratch_regs_engine_hung(adev, true);
> + amdgpu_atombios_scratch_regs_engine_hung(adev, true);
>
> - dev_info(adev->dev, "GPU mode1 reset\n");
> + dev_info(adev->dev, "GPU mode1 reset\n");
>
> - /* disable BM */
> - pci_clear_master(adev->pdev);
> + /* disable BM */
> + pci_clear_master(adev->pdev);
>
> - amdgpu_device_cache_pci_state(adev->pdev);
> + amdgpu_device_cache_pci_state(adev->pdev);
>
> - if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
> - dev_info(adev->dev, "GPU smu mode1 reset\n");
> - ret = amdgpu_dpm_mode1_reset(adev);
> - } else {
> - dev_info(adev->dev, "GPU psp mode1 reset\n");
> - ret = psp_gpu_reset(adev);
> - }
> + if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
> + dev_info(adev->dev, "GPU smu mode1 reset\n");
> + ret = amdgpu_dpm_mode1_reset(adev);
> + } else {
> + dev_info(adev->dev, "GPU psp mode1 reset\n");
> + ret = psp_gpu_reset(adev);
> + }
>
> - if (ret)
> - dev_err(adev->dev, "GPU mode1 reset failed\n");
> + if (ret)
> + dev_err(adev->dev, "GPU mode1 reset failed\n");
>
> - amdgpu_device_load_pci_state(adev->pdev);
> + amdgpu_device_load_pci_state(adev->pdev);
>
> - /* wait for asic to come out of reset */
> - for (i = 0; i < adev->usec_timeout; i++) {
> - u32 memsize = adev->nbio.funcs->get_memsize(adev);
> + /* wait for asic to come out of reset */
> + for (i = 0; i < adev->usec_timeout; i++) {
> + u32 memsize = adev->nbio.funcs->get_memsize(adev);
>
> - if (memsize != 0xffffffff)
> - break;
> - udelay(1);
> - }
> + if (memsize != 0xffffffff)
> + break;
> + udelay(1);
> + }
>
> - amdgpu_atombios_scratch_regs_engine_hung(adev, false);
> - return ret;
> + amdgpu_atombios_scratch_regs_engine_hung(adev, false);
> + return ret;
> }
>
> int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 03e928123d71..ee3d241195a2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -1661,7 +1661,7 @@ static const u16 amdgpu_unsupported_pciidlist[] = {
> };
>
> static const struct pci_device_id pciidlist[] = {
> -#ifdef CONFIG_DRM_AMDGPU_SI
> +#ifdef CONFIG_DRM_AMDGPU_SI
> {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
> {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
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