[PATCH V2] drm/amdgpu/gfx11: update gpu_clock_counter logic

[Alex Deucher]

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On Tue, Apr 11, 2023 at 5:14 PM Alex Deucher <alexander.deucher at amd.com> wrote:
>
> This code was written prior to previous updates to this
> logic for other chips.  The RSC registers are part of
> SMUIO which is an always on block so there is no need
> to disable gfxoff.  Additionally add the carryover and
> preemption checks.
>
> v2: rebase
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 107c487c0c37..00a06d353abd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4673,24 +4673,27 @@ static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>         uint64_t clock;
>         uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
>
> -       amdgpu_gfx_off_ctrl(adev, false);
> -       mutex_lock(&adev->gfx.gpu_clock_mutex);
>         if (amdgpu_sriov_vf(adev)) {
> +               amdgpu_gfx_off_ctrl(adev, false);
> +               mutex_lock(&adev->gfx.gpu_clock_mutex);
>                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
>                 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
>                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
>                 if (clock_counter_hi_pre != clock_counter_hi_after)
>                         clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
> +               mutex_unlock(&adev->gfx.gpu_clock_mutex);
> +               amdgpu_gfx_off_ctrl(adev, true);
>         } else {
> +               preempt_disable();
>                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
>                 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
>                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
>                 if (clock_counter_hi_pre != clock_counter_hi_after)
>                         clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
> +               preempt_enable();
>         }
>         clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
> -       mutex_unlock(&adev->gfx.gpu_clock_mutex);
> -       amdgpu_gfx_off_ctrl(adev, true);
> +
>         return clock;
>  }
>
> --
> 2.39.2
>