[PATCH] drm/amdgpu: disable SDMA WPTR_POLL_ENABLE for SR-IOV

[Deucher, Alexander]

[AMD Official Use Only - General]

> -----Original Message-----
> From: Horace Chen <horace.chen at amd.com>
> Sent: Thursday, April 27, 2023 2:24 AM
> To: amd-gfx at lists.freedesktop.org
> Cc: Andrey Grodzovsky <Andrey.Grodzovsky at amd.com>; Quan, Evan
> <Evan.Quan at amd.com>; Chen, Horace <Horace.Chen at amd.com>; Koenig,
> Christian <Christian.Koenig at amd.com>; Deucher, Alexander
> <Alexander.Deucher at amd.com>; Xiao, Jack <Jack.Xiao at amd.com>; Zhang,
> Hawking <Hawking.Zhang at amd.com>; Liu, Monk <Monk.Liu at amd.com>;
> Xu, Feifei <Feifei.Xu at amd.com>; Chang, HaiJun <HaiJun.Chang at amd.com>
> Subject: [PATCH] drm/amdgpu: disable SDMA WPTR_POLL_ENABLE for SR-
> IOV
> 
> [Why]
> This WPTR_POLL_ENABLE is a hardware contigious polling which will cause
> FCLK and UCLK to keep on a high level.
> Mostly its case can be covered by F32_WPTR_POLL_ENABLE which polls by
> firmware.
> So to save power, SR-IOV also needs to disable this bit
> 
> Signed-off-by: Horace Chen <horace.chen at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index eb722830531f..3d9a80511a45 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -510,10 +510,7 @@ static int sdma_v6_0_gfx_resume(struct
> amdgpu_device *adev)
>  		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
> 
>  		rb_cntl = REG_SET_FIELD(rb_cntl,
> SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
> -		if (amdgpu_sriov_vf(adev))
> -			rb_cntl = REG_SET_FIELD(rb_cntl,
> SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 1);
> -		else
> -			rb_cntl = REG_SET_FIELD(rb_cntl,
> SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
> +		rb_cntl = REG_SET_FIELD(rb_cntl,
> SDMA0_QUEUE0_RB_CNTL,
> +WPTR_POLL_ENABLE, 0);
>  		rb_cntl = REG_SET_FIELD(rb_cntl,
> SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
> 
>  		WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i,
> regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
> --
> 2.34.1