[PATCH 1/2] drm/amdgpu: update mall info v2 from discovery
Lazar, Lijo
lijo.lazar at amd.com
Thu Aug 17 06:41:59 UTC 2023
On 8/17/2023 9:02 AM, Le Ma wrote:
> Mall info v2 is introduced in ip discovery
>
> Change-Id: Ia2e49e7679c578065f85059a077fc08c9f84615c
> Signed-off-by: Le Ma <le.ma at amd.com>
> Reviewed-by: Shiwu Zhang <shiwu.zhang at amd.com>
Series is -
Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>
Thanks,
Lijo
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 5 +++++
> drivers/gpu/drm/amd/include/discovery.h | 8 +++++++-
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> index 9d8d08daca57..f4cd43ce251b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
> @@ -1478,6 +1478,7 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
>
> union mall_info {
> struct mall_info_v1_0 v1;
> + struct mall_info_v2_0 v2;
> };
>
> static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
> @@ -1518,6 +1519,10 @@ static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
> adev->gmc.mall_size = mall_size;
> adev->gmc.m_half_use = half_use;
> break;
> + case 2:
> + mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc);
> + adev->gmc.mall_size = mall_size_per_umc * adev->gmc.num_umc;
> + break;
> default:
> dev_err(adev->dev,
> "Unhandled MALL info table %d.%d\n",
> diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h
> index f43e29722ef7..b9884e576f98 100644
> --- a/drivers/gpu/drm/amd/include/discovery.h
> +++ b/drivers/gpu/drm/amd/include/discovery.h
> @@ -30,7 +30,7 @@
> #define GC_TABLE_ID 0x4347
> #define HARVEST_TABLE_SIGNATURE 0x56524148
> #define VCN_INFO_TABLE_ID 0x004E4356
> -#define MALL_INFO_TABLE_ID 0x4D414C4C
> +#define MALL_INFO_TABLE_ID 0x4C4C414D
>
> typedef enum
> {
> @@ -312,6 +312,12 @@ struct mall_info_v1_0 {
> uint32_t reserved[5];
> };
>
> +struct mall_info_v2_0 {
> + struct mall_info_header header;
> + uint32_t mall_size_per_umc;
> + uint32_t reserved[8];
> +};
> +
> #define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
>
> struct vcn_info_header {
More information about the amd-gfx
mailing list