[PATCH v2] drm/amdgpu : Updated TCP/UTCL1 programming

[Lazar, Lijo]

On 8/21/2023 6:17 PM, Mangesh Gadre wrote:
> It is required for TCP/UTCL1 thrashing
> 

Description looks a bit odd. You may rephrase as 'Update TCP/UTCL1 
thrashing control settings'.

Reviewed-by: Lijo Lazar <lijo.lazar at amd.com>

Thanks,
Lijo

> v2: updated rev_id check
> 
> Signed-off-by: Mangesh Gadre <Mangesh.Gadre at amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> index 93590adf2b04..8b84ca80d80b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
> @@ -203,6 +203,9 @@ static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
>   		if (adev->rev_id == 0) {
>   			WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL1,
>   					      REDUCE_FIFO_DEPTH_BY_2, 2);
> +		} else {
> +			WREG32_FIELD15_PREREG(GC, dev_inst, TCP_UTCL1_CNTL2,
> +						SPARE, 0x1);
>   		}
>   	}
>   }