[PATCH] drm/amdgpu: access RLC_SPM_MC_CNTL through MMIO in SRIOV

[Alex Deucher]

Acked-by: Alex Deucher <alexander.deucher at amd.com>

On Mon, Aug 28, 2023 at 2:50 AM ZhenGuo Yin <zhenguo.yin at amd.com> wrote:
>
> Register RLC_SPM_MC_CNTL is not blocked by L1 policy, VF can
> directly access it through MMIO.
>
> Signed-off-by: ZhenGuo Yin <zhenguo.yin at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 ++--------
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 ++--------
>  2 files changed, 4 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 0aee9c8288a2..65619f73f717 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7901,18 +7901,12 @@ static void gfx_v10_0_update_spm_vmid_internal(struct amdgpu_device *adev,
>
>         /* not for *_SOC15 */
>         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
> -       if (amdgpu_sriov_is_pp_one_vf(adev))
> -               data = RREG32_NO_KIQ(reg);
> -       else
> -               data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
> +       data = RREG32_NO_KIQ(reg);
>
>         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
>         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
>
> -       if (amdgpu_sriov_is_pp_one_vf(adev))
> -               WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
> -       else
> -               WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
> +       WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
>  }
>
>  static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned int vmid)
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index b0c32521efdc..7f8c5c6fd36e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4989,18 +4989,12 @@ static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
>         amdgpu_gfx_off_ctrl(adev, false);
>
>         reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
> -       if (amdgpu_sriov_is_pp_one_vf(adev))
> -               data = RREG32_NO_KIQ(reg);
> -       else
> -               data = RREG32(reg);
> +       data = RREG32_NO_KIQ(reg);
>
>         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
>         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
>
> -       if (amdgpu_sriov_is_pp_one_vf(adev))
> -               WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
> -       else
> -               WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
> +       WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
>
>         amdgpu_gfx_off_ctrl(adev, true);
>  }
> --
> 2.35.1
>