[PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

[Zuo, Jerry]

[AMD Official Use Only - General]


Series is:

Reviewed-By: Fangzhi Zuo <jerry.zuo at amd.com>

________________________________
发件人: Mahfooz, Hamza <Hamza.Mahfooz at amd.com>
发送时间: 星期四, 八月 31, 2023 3:39:04 下午
收件人: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
抄送: Zuo, Jerry <Jerry.Zuo at amd.com>; Mahfooz, Hamza <Hamza.Mahfooz at amd.com>; stable at vger.kernel.org <stable at vger.kernel.org>; Wentland, Harry <Harry.Wentland at amd.com>; Li, Sun peng (Leo) <Sunpeng.Li at amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>; Pan, Xinhui <Xinhui.Pan at amd.com>; David Airlie <airlied at gmail.com>; Daniel Vetter <daniel at ffwll.ch>; Lei, Jun <Jun.Lei at amd.com>; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas at amd.com>; Liu, Wenjing <Wenjing.Liu at amd.com>; Lee, Alvin <Alvin.Lee2 at amd.com>; Kim, Sung joon <Sungjoon.Kim at amd.com>; Miess, Daniel <Daniel.Miess at amd.com>; Teeger, Gabe <Gabe.Teeger at amd.com>; dri-devel at lists.freedesktop.org <dri-devel at lists.freedesktop.org>; linux-kernel at vger.kernel.org <linux-kernel at vger.kernel.org>
主题: [PATCH v2 1/2] Revert "drm/amd/display: Remove v_startup workaround for dcn3+"

This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e.

We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+
ASICs otherwise it can cause DP to HDMI 2.1 PCONs to fail to light up.

Cc: stable at vger.kernel.org
Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809
Signed-off-by: Hamza Mahfooz <hamza.mahfooz at amd.com>
---
 .../drm/amd/display/dc/dml/dcn20/dcn20_fpu.c  | 24 ++++---------------
 1 file changed, 4 insertions(+), 20 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index 0989a0152ae8..1bfdf0271fdf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1099,6 +1099,10 @@ void dcn20_calculate_dlg_params(struct dc *dc,
                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
+               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
+                       dcn20_adjust_freesync_v_startup(
+                               &context->res_ctx.pipe_ctx[i].stream->timing,
+                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);

                 pipe_idx++;
         }
@@ -1927,7 +1931,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
         int vlevel = 0;
         int pipe_split_from[MAX_PIPES];
         int pipe_cnt = 0;
-       int i = 0;
         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
         DC_LOGGER_INIT(dc->ctx->logger);

@@ -1951,15 +1954,6 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               if (!context->res_ctx.pipe_ctx[i].stream)
-                       continue;
-               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-                       dcn20_adjust_freesync_v_startup(
-                               &context->res_ctx.pipe_ctx[i].stream->timing,
-                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-       }
-
         BW_VAL_TRACE_END_WATERMARKS();

         goto validate_out;
@@ -2232,7 +2226,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
         int vlevel = 0;
         int pipe_split_from[MAX_PIPES];
         int pipe_cnt = 0;
-       int i = 0;
         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
         DC_LOGGER_INIT(dc->ctx->logger);

@@ -2261,15 +2254,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);

-       for (i = 0; i < dc->res_pool->pipe_count; i++) {
-               if (!context->res_ctx.pipe_ctx[i].stream)
-                       continue;
-               if (context->res_ctx.pipe_ctx[i].stream->adaptive_sync_infopacket.valid)
-                       dcn20_adjust_freesync_v_startup(
-                               &context->res_ctx.pipe_ctx[i].stream->timing,
-                               &context->res_ctx.pipe_ctx[i].pipe_dlg_param.vstartup_start);
-       }
-
         BW_VAL_TRACE_END_WATERMARKS();

         goto validate_out;
--
2.41.0


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