[PATCH 0/4] Extend amdgpu_device_pcie_dynamic_switching_supported()

[Mario Limonciello]

amdgpu_device_pcie_dynamic_switching_supported() currently only covers
SMU13. It sets up the pcietables so that effectively DPM can't change
speed or lane width dynamically on problematic hosts.

Earlier quirks to SMU11 did a similar solution by looking at specific
PCI IDs typically paired with problematic products.

Even earlier dGPUS used in Intel Alder Lake and Rocket lake adopted
similar solutions that would turn off DPM.

These all come down to the same fundmental problem; Intel hosts can't
handle these features. There is nothing to stop someone from taking a
Navi14 and putting it into Sapphire Rapids system and hitting the
same problem that was observed when it was placed into an Alder
Lake-S system.

Because of this; drop all the specific Intel model + AMD dGPU matching
across the driver and instead match ALL Intel hosts to do these
quirks of setting PCIe override parameters or turning off DPM.

If a new Intel host does work well with dynamic speed switching we
can later adjust amdgpu_device_pcie_dynamic_switching_supported() to
have a switch/case where we allow list those hosts, or enumerate all
the broken ones and disallow list them.

Mario Limonciello (4):
  drm/amd: Move helper for dynamic speed switch check out of smu13
  drm/amd: Align SMU11 SMU_MSG_OverridePcieParameters implementation
    with SMU13
  drm/amd: Use amdgpu_device_pcie_dynamic_switching_supported() for SMU7
  drm/amd: Drop amdgpu_device_aspm_support_quirk()

 drivers/gpu/drm/amd/amdgpu/amdgpu.h           |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_device.c    | 30 ++++---
 drivers/gpu/drm/amd/amdgpu/nv.c               |  5 +-
 drivers/gpu/drm/amd/amdgpu/vi.c               |  5 +-
 .../drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c   | 14 +--
 .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c   | 89 ++++---------------
 .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c    | 21 +----
 7 files changed, 49 insertions(+), 117 deletions(-)

-- 
2.34.1