[PATCH] drm/amdgpu: Program xcp_ctl registers as needed

[Zhang, Hawking]

[AMD Official Use Only - General]

Reviewed-by: Hawking Zhang <Hawking.Zhang at amd.com>

Regards,
Hawking
-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar at amd.com>
Sent: Thursday, July 20, 2023 13:56
To: amd-gfx at lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Morris <Shiwu.Zhang at amd.com>
Subject: [PATCH] drm/amdgpu: Program xcp_ctl registers as needed

XCP_CTL register is expected to be programmed by firmware. Under certain conditions FW may not have programmed it correctly. As a workaround, program it when FW has not programmed the right values.

Signed-off-by: Lijo Lazar <lijo.lazar at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 23 ++++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 738226ed6e50..c567be88c47d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -621,7 +621,7 @@ static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                int num_xccs_per_xcp)
 {
        int ret, i, num_xcc;
-       u32 tmp = 0;
+       u32 tmp = 0, regval;

        if (adev->psp.funcs) {
                ret = psp_spatial_partition(&adev->psp, @@ -629,23 +629,24 @@ static int gfx_v9_4_3_switch_compute_partition(struct amdgpu_device *adev,
                                                    num_xccs_per_xcp);
                if (ret)
                        return ret;
-       } else {
-               num_xcc = NUM_XCC(adev->gfx.xcc_mask);
+       }
+
+       num_xcc = NUM_XCC(adev->gfx.xcc_mask);

-               for (i = 0; i < num_xcc; i++) {
-                       tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
-                                           num_xccs_per_xcp);
-                       tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
-                                           i % num_xccs_per_xcp);
+       for (i = 0; i < num_xcc; i++) {
+               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, NUM_XCC_IN_XCP,
+                                   num_xccs_per_xcp);
+               tmp = REG_SET_FIELD(tmp, CP_HYP_XCP_CTL, VIRTUAL_XCC_ID,
+                                   i % num_xccs_per_xcp);
+               regval = RREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL);
+               if (regval != tmp)
                        WREG32_SOC15(GC, GET_INST(GC, i), regCP_HYP_XCP_CTL,
                                     tmp);
-               }
-               ret = 0;
        }

        adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;

-       return ret;
+       return 0;
 }

 static int gfx_v9_4_3_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
--
2.25.1