[PATCH] drm/amd/display: Only use ODM2:1 policy for high pixel rate displays

[Rodrigo Siqueira Jordao]

On 6/6/23 09:47, Aurabindo Pillai wrote:
> We only gain a benefit of using the ODM2:1 dynamic policy if it allow us
> to decrease DISPCLK to use the VMIN freq.  If the display config can
> already achieve VMIN DISPCLK freq without ODM2:1, don't apply the
> policy.
> 
> This patch was reverted but that causes some IGT regressions. To
> unblock, the patch is being applied again until IGT failures are
> fixed.
> 
> Signed-off-by: Alvin Lee <Alvin.Lee2 at amd.com>
> Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
> Signed-off-by: Aurabindo Pillai <aurabindo.pillai at amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 +
>   drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 +
>   2 files changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> index 8d68f02f5147..2e6b39fe2613 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
> @@ -1918,6 +1918,7 @@ int dcn32_populate_dml_pipes_from_context(
>   				context->stream_status[0].plane_count == 1 &&
>   				!dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) &&
>   				is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) &&
> +				pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ &&
>   				dc->debug.enable_single_display_2to1_odm_policy &&
>   				!vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr
>   			pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1;
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> index 80bebdf43eca..2f34f01b3ea1 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
> @@ -40,6 +40,7 @@
>   #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq
>   #define SUBVP_HIGH_REFRESH_LIST_LEN 3
>   #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800
> +#define DCN3_2_VMIN_DISPCLK_HZ 717000000
>   
>   #define TO_DCN32_RES_POOL(pool)\
>   	container_of(pool, struct dcn32_resource_pool, base)

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>